公开(公告)号：US11996343B2

公开(公告)日：2024-05-28

申请号：US17114219

申请日：2020-12-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/34 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/768 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L21/74

CPC classification number: H01L23/367 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/76895 ,  H01L23/3735 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L27/0248 ,  H01L21/743 ,  H01L23/3677 ,  H01L2224/48463

Abstract: An integrated circuit has a substrate that includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

公开(公告)号：US20240153938A1

公开(公告)日：2024-05-09

申请号：US18148658

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Neil Gibson ,  Jerry L. Doorenbos ,  Gerald Gradl ,  VIOLA Schaeffer ,  Archana Venugopal ,  Henry L. Edwards

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L27/0207 ,  H01L27/088 ,  H01L27/1207

Abstract: An integrated circuit includes a first transistor array over a semiconductor substrate and is distributed among a first plurality of first transistor banks. A second transistor array in or over the semiconductor substrate is distributed among a second plurality of second transistor banks. A first one of the first transistor banks is located between a first one and a second one of the second transistor banks, and the second one of the second transistor banks is located between the first one of the first transistor banks and a second one of the first transistor banks. The first transistor array and the second transistor array may be alternately operated to implement a voltage-conversion integrated circuit.

公开(公告)号：US11370662B2

公开(公告)日：2022-06-28

申请号：US16230070

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luigi Colombo ,  Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal

IPC: C01B21/064 ,  C23C16/34 ,  C23C18/32 ,  C23C18/16 ,  C23C18/36 ,  C23C18/28 ,  C23C18/30 ,  C23C18/20 ,  G03F1/60 ,  G03F1/20 ,  C23C18/38 ,  C23C18/42

Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of hexagonal boron nitride (h-BN) tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing an h-BN precursor on the metal microlattice, converting the h-BN precursor to h-BN, and removing the metal microlattice.

公开(公告)号：US10529641B2

公开(公告)日：2020-01-07

申请号：US15361390

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/373 ,  H01L23/522

Abstract: An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.

公开(公告)号：US10475725B2

公开(公告)日：2019-11-12

申请号：US15807370

申请日：2017-11-08

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Archana Venugopal

IPC: H01L23/42 ,  H01L49/02 ,  H01L23/485 ,  H01L23/522 ,  H01L21/768

Abstract: An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.

公开(公告)号：US10468324B2

公开(公告)日：2019-11-05

申请号：US15183896

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Sameer Pendharkar

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/522 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/48 ,  H01L21/02 ,  H01L23/00

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

公开(公告)号：US20190273166A1

公开(公告)日：2019-09-05

申请号：US15910817

申请日：2018-03-02

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Luigi Colombo

IPC: H01L29/786 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/49 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02

Abstract: A microelectronic device includes a gated graphene component. The gated graphene component has a graphitic layer containing one or more layers of graphene. The graphitic layer has a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region. A patterned hexagonal boron nitride (hBN) layer is disposed on the graphitic layer above the channel region. A gate is located over the patterned hBN layer above the channel region. A first connection is disposed on the graphitic layer in the first contact region, and a second connection is disposed on the graphitic layer in the second contact region. The patterned hBN layer does not extend completely under the first connection or under the second connection. A method of forming the gated graphene component in the microelectronic device is disclosed.

公开(公告)号：US10304967B1

公开(公告)日：2019-05-28

申请号：US15910854

申请日：2018-03-02

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Luigi Colombo ,  Arup Polley

IPC: H01L31/0312 ,  H01L29/786 ,  H01L29/20 ,  H01L29/267 ,  H01L29/49 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/16

Abstract: A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.

公开(公告)号：US10256188B2

公开(公告)日：2019-04-09

申请号：US15361401

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L27/08 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/288 ,  H01L21/285 ,  H01L21/324 ,  H01L21/3105 ,  H01L23/367 ,  H01L23/373

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

公开(公告)号：US20180308696A1

公开(公告)日：2018-10-25

申请号：US15496814

申请日：2017-04-25

Applicant: Texas Instruments Incorporated

Inventor： Luigi Colombo ,  Archana Venugopal

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/786 ,  H01L29/45

CPC classification number: H01L21/043 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/78618 ,  H01L29/78684

Abstract: An electronic device has a graphene layer having one or more atomic layers of graphene, with low resistance contacts that includes a carbon-doped metal layer directly on the graphene layer. The electronic device is formed by forming a carbon-doped metal layer on a substrate layer of the electronic device. The carbon-doped metal layer is subsequently heated to a temperature above which carbon in the carbon-doped metal layer becomes mobile, and subsequently cooled. The carbon in the carbon-doped metal forms the graphene layer under the carbon-doped metal layer and over the substrate layer. The carbon-doped metal layer is removed from an area outside of a contact area, leaving the carbon-doped metal in the contact area to provide a contact layer to the graphene layer.