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    Processing device with vector transformation execution
    55.
    发明授权
    Processing device with vector transformation execution 有权

    公开(公告)号：US11327761B2

    公开(公告)日：2022-05-10

    申请号：US16881327

    申请日：2020-05-22

    Applicant: Texas Instruments Incorporated

    Inventor： Mujibur Rahman ,  Timothy David Anderson ,  Joseph Zbiciak

    IPC: G06F9/30 ,  G06F9/38

    Abstract: An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.

    Three-term predictive adder and/or subtracter
    59.
    发明授权
    Three-term predictive adder and/or subtracter 有权
    三项预测加法器和/或减法器

    公开(公告)号：US09448767B2

    公开(公告)日：2016-09-20

    申请号：US14192102

    申请日：2014-02-27

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy D. Anderson ,  Mujibur Rahman ,  Kai Chirca

    IPC: G06F7/50 ,  G06F7/57 ,  G06F7/505 ,  G06F7/506

    CPC classification number: G06F7/57 ,  G06F7/5055 ,  G06F7/506

    Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.

    Abstract translation: 预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。 预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示纹波部分 的位数在电位和。 预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

    Vector SIMD VLIW Data Path Architecture
    60.
    发明申请
    Vector SIMD VLIW Data Path Architecture 审中-公开
    矢量SIMD VLIW数据路径架构

    公开(公告)号：US20150154024A1

    公开(公告)日：2015-06-04

    申请号：US14327084

    申请日：2014-07-09

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mujibur Rahman ,  Joseph Raymond Michael Zbiciak ,  Eric Biscondi ,  Peter Dent ,  Jelena Milanovic ,  Ashish Shrivastava

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30112 ,  G06F9/3893

    Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

    Abstract translation: 特别适用于各种操作数宽度和数据大小的单指令多数据（SIMD）操作的超长指令字（VLIW）数字信号处理器。 向量比较指令比较第一和第二操作数并存储比较位。 伴随向量条件指令根据相应谓词数据寄存器位的状态执行条件操作。 谓词单元对包括一元操作和二进制操作的至少一个谓词数据寄存器中的数据执行数据处理操作。 谓词单元还可以在通用数据寄存器文件和谓词数据寄存器文件之间传送数据。

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