公开(公告)号：US20160141298A1

公开(公告)日：2016-05-19

申请号：US14547251

申请日：2014-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/06

CPC classification number: H01L27/11563 ,  H01L21/28008 ,  H01L21/76229 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/4234 ,  H01L29/66545

Abstract: The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG integrated circuit. In one embodiment, an STI region underlying a memory contact pad region is recessed to make the STI surface substantially co-planar with the rest of the semiconductor substrate. The recess allows formation of thicker memory contact pad structures. The thicker polysilicon on these contact pad structures prevents contact over-etching and thus reduces the Rc of contacts formed thereon.

Abstract translation: 本发明涉及用于在嵌入式闪速存储器HKMG集成电路上减少接触过蚀刻和高接触电阻（Rc）的结构和方法。 在一个实施例中，存储器接触焊盘区域下面的STI区域是凹进的，以使STI表面与半导体衬底的其余部分基本上共面。 该凹槽允许形成更厚的记忆接触垫结构。 这些接触焊盘结构上较厚的多晶硅防止接触过蚀刻，从而减少形成在其上的触点的Rc。

公开(公告)号：US20160056250A1

公开(公告)日：2016-02-25

申请号：US14481987

申请日：2014-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry Hak-Lay Chuang ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Ya-Chen Kao

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115 ,  H01L27/105

CPC classification number: H01L29/42344 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad.

Abstract translation: 本公开的一些实施例提供了一种用于嵌入式闪存设备的集成电路（IC）。 IC包括具有存储单元门的闪存单元。 硅化物接触焊盘设置在存储单元栅极的凹部中。 硅化物接触焊盘的顶表面相对于存储单元栅极的顶表面凹陷。 电介质侧壁间隔物从凹槽的侧壁从存储单元栅极的顶表面延伸到硅化物接触焊盘的顶表面。

公开(公告)号：US20150263010A1

公开(公告)日：2015-09-17

申请号：US14210796

申请日：2014-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chin-Yi Huang ,  Shih-Chang Liu ,  Chang-Ming Wu

IPC: H01L27/11 ,  H01L27/115

CPC classification number: H01L27/11534 ,  H01L27/11521 ,  H01L29/66545

Abstract: The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary.

Abstract translation: 本公开涉及一种在采用替代门技术的HKMG集成电路中嵌入ESF3存储器的方法。 ESF3存储器形成在凹陷的衬底上，防止在ILD层执行的CMP工艺期间对存储器控制栅极的损坏。 在存储单元和外围电路边界之间的过渡区域中也形成非对称隔离区。

公开(公告)号：US20240147716A1

公开(公告)日：2024-05-02

申请号：US18404676

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H10B41/30 ,  H01L21/28 ,  H01L21/306 ,  H01L21/321 ,  H01L21/8234 ,  H01L27/105 ,  H01L29/66 ,  H10B41/49 ,  H10B43/00 ,  H10B43/30

CPC classification number: H10B41/30 ,  H01L21/30604 ,  H01L21/3212 ,  H01L21/823462 ,  H01L27/105 ,  H01L29/40114 ,  H01L29/66545 ,  H10B41/49 ,  H10B43/00 ,  H10B43/30 ,  H10B10/18

Abstract: An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

公开(公告)号：US20230299041A1

公开(公告)日：2023-09-21

申请号：US17748547

申请日：2022-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Haklay Chuang ,  Yuan-Jen Lee ,  Fang-Lan Chu ,  Wei Cheng Wu ,  Nuo Xu

IPC: H01L23/00 ,  H01L23/544

CPC classification number: H01L24/80 ,  H01L23/544 ,  H01L24/08 ,  H01L2223/54426 ,  H01L2224/0217 ,  H01L2224/08145 ,  H01L2224/8013 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: In an embodiment, a structure includes: a first device including a first dielectric layer and a first alignment mark in the first dielectric layer, the first alignment mark including a first magnetic cross, the first magnetic cross having a first north pole and a first south pole; and a second device including a second dielectric layer and a second alignment mark in the second dielectric layer, the second alignment mark including a second magnetic cross, the second magnetic cross having a second north pole and a second south pole, the first north pole aligned with the second south pole, the first south pole aligned with the second north pole, the first dielectric layer bonded to the second dielectric layer by dielectric-to-dielectric bonds, the first alignment mark bonded to the second alignment mark by metal-to-metal bonds.

公开(公告)号：US11751400B2

公开(公告)日：2023-09-05

申请号：US17230191

申请日：2021-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Pai Chi Chou

IPC: H01L21/762 ,  H10B51/30 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H10B51/30 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/42364 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a first doped region and a second doped region within a substrate. A ferroelectric material is arranged over the substrate and laterally between the first doped region and the second doped region. A conductive electrode is over the ferroelectric material and between sidewalls of the ferroelectric material. One or more sidewall spacers are arranged along opposing sides of the ferroelectric material. A dielectric layer continuously and laterally extends from directly below the one or more sidewall spacers to directly below the ferroelectric material.

公开(公告)号：US11706917B2

公开(公告)日：2023-07-18

申请号：US17094758

申请日：2020-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Wei Cheng Wu

IPC: H10B41/47 ,  H01L29/423 ,  H01L21/285 ,  H01L29/788 ,  H01L21/306 ,  H01L29/66 ,  H10B41/30 ,  H10B99/00

CPC classification number: H10B41/47 ,  H01L21/28518 ,  H01L21/30625 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/30 ,  H10B99/00

Abstract: A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

公开(公告)号：US11672124B2

公开(公告)日：2023-06-06

申请号：US17184953

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H10B43/40 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L27/11573 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L27/11573 ,  H01L21/823462 ,  H01L27/092 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66545 ,  H01L27/088

Abstract: The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.

公开(公告)号：US11264396B2

公开(公告)日：2022-03-01

申请号：US16666731

申请日：2019-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H01L27/11517 ,  H01L29/788 ,  H01L29/66 ,  G11C16/04 ,  H01L27/105 ,  H01L27/108

Abstract: Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.

公开(公告)号：US11239246B2

公开(公告)日：2022-02-01

申请号：US16848921

申请日：2020-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Wei Cheng Wu ,  Chih-Pin Huang

IPC: H01L27/11548 ,  H01L29/423 ,  H01L21/768 ,  H01L29/66 ,  H01L21/033 ,  H01L23/532 ,  H01L27/11524 ,  H01L21/762 ,  H01L21/321 ,  H01L27/11534 ,  H01L29/51 ,  H01L27/11575 ,  H01L21/8234

Abstract: Various embodiments of the present application are directed to a method of forming an integrated circuit (IC). An isolation structure is formed between a logic region and a memory region of a substrate. A dummy structure is formed on the isolation structure and defines a dummy sidewall of the dummy structure facing the logic region. A boundary sidewall spacer is formed covering the dummy structure and at least partially defines a boundary sidewall of the boundary sidewall spacer facing the logic region. A protecting dielectric layer is formed on a top surface of the boundary sidewall spacer by converting an uppermost portion of the boundary sidewall spacer to the protecting dielectric layer. The protecting dielectric layer is removed, and a logic device structure is formed on the logic region.