公开(公告)号：US20230328948A1

公开(公告)日：2023-10-12

申请号：US18333197

申请日：2023-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H10B10/00 ,  H01L27/092 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413

CPC classification number: H10B10/12 ,  H01L27/0924 ,  G11C11/413 ,  G11C11/412 ,  G11C11/419

Abstract: A semiconductor device includes first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, and first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction. The first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors. The first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected. The fifth active region is disposed between the second and third active regions.

公开(公告)号：US11737260B2

公开(公告)日：2023-08-22

申请号：US17034727

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang ,  Chia-En Huang

IPC: H01L21/321 ,  H10B20/20 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06

CPC classification number: H10B20/20 ,  H01L29/045 ,  H01L29/0692 ,  H01L29/66545

Abstract: A memory device includes a substrate, an active region, a first gate structure, a second gate structure, a first word line, and a second word line. The active region protrudes from a top surface of the substrate. The active region has at least one ring structure, in which when viewed from above, the ring structure has a first linear portion, a second linear portion, a first curved portion, and a second curved portion, the first curved portion connects first sides of the first and second linear portions, and the second curved portion connects second sides of the first and second linear portions. The first gate structure and the second gate structure are over the substrate and cross the active region. The first word line and the second word line are electrically connected to the first gate structure and the second gate structure, respectively.

公开(公告)号：US11475942B2

公开(公告)日：2022-10-18

申请号：US17154608

申请日：2021-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chia-Hao Pao ,  Choh Fei Yeap ,  Yu-Kuan Lin ,  Kian-Long Lim

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/419

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

公开(公告)号：US11450673B2

公开(公告)日：2022-09-20

申请号：US16945146

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US11387240B2

公开(公告)日：2022-07-12

申请号：US16854772

申请日：2020-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC: H01L27/11 ,  G11C11/412 ,  H01L29/66 ,  H01L23/522 ,  H01L27/02 ,  H01L21/768

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

公开(公告)号：US20210398588A1

公开(公告)日：2021-12-23

申请号：US17154608

申请日：2021-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chia-Hao Pao ,  Choh Fei Yeap ,  Yu-Kuan Lin ,  Kian-Long Lim

IPC: G11C11/412 ,  G11C11/419 ,  H01L27/11

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

公开(公告)号：US20210391439A1

公开(公告)日：2021-12-16

申请号：US16901340

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Chih-Hsuan Chen ,  Yu-Kuan Lin

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/02

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.

公开(公告)号：US11056594B2

公开(公告)日：2021-07-06

申请号：US16908441

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/308 ,  H01L21/8238

Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate having a well pick-up region and an active region adjacent to the well pick-up region. The semiconductor device structure also includes a first fin structure with a first width and a third fin structure with a third width formed adjacent to each other in the well pick-up region and a second fin structure with a second width and a fourth fin structure with a fourth width formed adjacent to each other in the active region. The first width is different than the second width, the third width is different than the fourth width, and the first width is substantially equal to or greater than the third width.

公开(公告)号：US20210082475A1

公开(公告)日：2021-03-18

申请号：US16573769

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Lin Chen ,  Chao-Yuan Chang ,  Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: G11C5/06 ,  G06F17/50 ,  H01L23/522 ,  H01L27/11 ,  H01L27/092 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure, a source/drain, a first via that is disposed over the gate structure and the source/drain, and a first metal line having a more elevated vertical position than the first via in a cross-sectional view. The first via is electrically coupled to both the gate structure and the source/drain. The first metal line and the first via each extends in a first direction. A first distance separates the metal line from the via in a second direction different from the first direction. The first metal line includes a protruding portion that protrudes outwardly in the second direction.

公开(公告)号：US10943827B2

公开(公告)日：2021-03-09

申请号：US16867754

申请日：2020-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chun Keng ,  Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L21/311 ,  H01L21/3065

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure over a semiconductor substrate. A top surface of the first fin structure is closer to the semiconductor substrate than a top surface of the second fin structure. The semiconductor device structure also includes a first epitaxial structure on the first fin structure. The semiconductor device structure further includes a second epitaxial structure on the third fin structure. The first epitaxial structure is wider than the second epitaxial structure.