公开(公告)号：US20240339408A1

公开(公告)日：2024-10-10

申请号：US18745613

申请日：2024-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor structure includes a first redistribution structure, a first local interconnect component disposed on the first redistribution structure, and a first interconnect structure over a second side of the first local interconnect component. The first local interconnect component includes a first plurality of redistribution layers. The first plurality of redistribution layers includes a first plurality of conductive features on a first side of the first local interconnect component. Each of the first plurality of conductive features are coupled to respective conductive features of the first redistribution structure. The first interconnect structure includes a second plurality of conductive features and a third plurality of conductive features. The second plurality of conductive features are electrically coupled to the third plurality of conductive features through the first local interconnect component.

公开(公告)号：US12080563B2

公开(公告)日：2024-09-03

申请号：US17994841

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5226

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US12068297B2

公开(公告)日：2024-08-20

申请号：US18182852

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Jiun Yi Wu ,  Hsing-Kuo Hsia

IPC: H01L25/16 ,  G02B6/122 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L23/66 ,  H01L31/02 ,  H01L31/18 ,  H10B80/00

CPC classification number: H01L25/167 ,  G02B6/122 ,  H01L21/4857 ,  H01L21/76871 ,  H01L23/49833 ,  H01L23/5226 ,  H01L23/5385 ,  H01L23/66 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L31/02002 ,  H01L31/18 ,  H10B80/00 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/81 ,  H01L24/83 ,  H01L2223/6627 ,  H01L2224/02371 ,  H01L2224/13021 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2924/0635

Abstract: An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.

公开(公告)号：US11984375B2

公开(公告)日：2024-05-14

申请号：US18302589

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Ling Tsai ,  Jiun Yi Wu ,  Chien-Hsun Lee ,  Chung-Shi Liu

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/3121 ,  H01L23/49827 ,  H01L23/5384

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

公开(公告)号：US20240096812A1

公开(公告)日：2024-03-21

申请号：US18520958

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chien-Hsun Lee

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379

Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

公开(公告)号：US20240063177A1

公开(公告)日：2024-02-22

申请号：US18499920

申请日：2023-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Shang-Yun Hou

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/97 ,  H01L23/3114 ,  H01L23/49861 ,  H01L23/49827 ,  H01L2224/82896 ,  H01L2224/80895

Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.

公开(公告)号：US11894312B2

公开(公告)日：2024-02-06

申请号：US17869286

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chun-Chih Chuang ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Jiun Yi Wu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19106

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

公开(公告)号：US20240021511A1

公开(公告)日：2024-01-18

申请号：US18446229

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49833 ,  H01L23/49811 ,  H01L23/31 ,  H01L23/562 ,  H01L24/16 ,  H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2224/16227

Abstract: In an embodiment, a method for manufacturing a semiconductor device includes forming a redistribution structure on a carrier substrate, connecting a plurality of core substrates physically and electrically to the redistribution structure with a first anisotropic conductive film, the first anisotropic conductive film including a dielectric material and conductive particles, and pressing the plurality of core substrates and the redistribution structure together to form conductive paths between the plurality of core substrates and the redistribution structure with the conductive particles in the first anisotropic conductive film. The method also includes encapsulating the plurality of core substrates with an encapsulant. The method also includes and attaching an integrated circuit package to the redistribution structure, the redistribution structure being between the integrated circuit package and the plurality of core substrates, the integrated circuit package laterally overlapping a first core substrate and a second core substrate of the plurality of core substrates.

公开(公告)号：US20240021510A1

公开(公告)日：2024-01-18

申请号：US18362401

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894

Abstract: An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.

公开(公告)号：US20240021467A1

公开(公告)日：2024-01-18

申请号：US18363359

申请日：2023-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wei-Yu Chen ,  Jiun Yi Wu ,  Chung-Shi Liu ,  Chien-Hsun Lee

IPC: H01L21/768 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/76802 ,  H01L23/5384 ,  H01L21/56 ,  H01L23/31 ,  H01L23/5386 ,  H01L2021/60022

Abstract: A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.