-
51.发明授权公开(公告)号：US07045865B2
公开(公告)日：2006-05-16
申请号：US09960495
申请日：2001-09-24
CPC分类号： H01L27/0207 , H01L27/0629 , H01L27/0802 , H01L28/20
摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
摘要翻译： 本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。 有源区靠近电阻元件配置。 这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。
-
52.发明授权
公开(公告)号：US06069579A
公开(公告)日：2000-05-30
申请号：US131238
申请日：1998-08-07
摘要： An A/D converter simplifies its circuit configuration without deteriorating accuracy in A/D conversion. A circuit is formed of a folding and interpolation type. A gain-variable pre-amplifier group 11 amplifies each of reference voltages Vref1 to VrefN and an analog input voltage Vin, to output the result to a folding amplifier group 12, while a gain-variable pre-amplifier group 21 amplifies each of reference voltages Vrr1 to VrrJ and the analog input voltage Vin, to output the result to a comparator group 24. Each of pre-amplifiers constituting the gain-variable pre-amplifier groups 11 and 21 has an amplification factor that varies in upper and lower comparison periods according to a clock control signal .PHI.cnt.
摘要翻译： A / D转换器简化了其电路配置，而不会降低A / D转换的精度。 电路由折叠和内插形式组成。 增益可变前置放大器组11放大每个参考电压Vref1至VrefN和模拟输入电压Vin，以将结果输出到折叠放大器组12，而增益可变的前置放大器组21放大每个参考电压 Vrr1至VrrJ和模拟输入电压Vin，将结果输出到比较器组24.构成增益可变前置放大器组11和21的每个前置放大器具有在上和下比较周期内变化的放大系数， 到时钟控制信号PHI cnt。
-
53.发明授权Analog/digital converter and voltage comparator capable of fast producing of output offset voltage 失效模拟/数字转换器和电压比较器能够快速产生输出失调电压
公开(公告)号：US5966088A
公开(公告)日：1999-10-12
申请号：US982279
申请日：1997-12-01
申请人： Osamu Matsumoto , Toshio Kumamoto
发明人： Osamu Matsumoto , Toshio Kumamoto
CPC分类号： H03M1/1023 , H03M1/168
摘要： An A/D converter includes a sample-hold circuit, A/D converting stages connected in series to the sample-hold circuit, and an encoder/latch circuit which adds 3-bit digital signals issued from the A/D converting stages to each other for outputting a signal of 9 bits. The sample-hold circuit and the A/D converting stages each include a differential amplifier. Differential outputs of each differential amplifier are short-circuited for a predetermined initial period in each sampling period.
摘要翻译： A / D转换器包括采样保持电路，与采样保持电路串联连接的A / D转换级，以及编码器/锁存电路，其将从A / D转换级发出的3位数字信号加到每个 另一个用于输出9位的信号。 采样保持电路和A / D转换级各自包括差分放大器。 在每个采样周期中，每个差分放大器的差分输出在预定的初始周期短路。
-
公开(公告)号：US5696511A
公开(公告)日：1997-12-09
申请号：US738585
申请日：1996-10-29
申请人： Osamu Matsumoto , Toshio Kumamoto
发明人： Osamu Matsumoto , Toshio Kumamoto
CPC分类号： H03M1/0695 , H03M1/167
摘要： In a pipeline type A/D converter, a sample/hold.cndot.subtracter circuit of an A/D converter block of a first stage samples an analog voltage and outputs an offset voltage at a first phase, and subtracts an output voltage of an A/D converter from the sampled analog voltage in a second phase. An A/D converter of an A/D converter block of a succeeding stage subtracts the output voltage of the sample/hold.cndot.subtracter circuit of the first phase from the output voltage of the sample hold.cndot.subtracter circuit of the second phase, and converts the subtracted result into a digital code. The influence of an offset of a differential amplifier included in the sample/hold.cndot.subtracter circuit is removed so that A/D conversion of high accuracy is allowed.
摘要翻译： 在流水线型A / D转换器中，第一级的A / D转换器模块的采样/保持减法器电路对模拟电压进行采样，并在第一阶段输出偏移电压，并且减去A / D转换器从第二阶段的采样模拟电压。 后级的A / D转换器模块的A / D转换器从第二相的采样保持电路的输出电压中减去第一相的采样/保持电路的输出电压，并将其转换 减去结果成数字代码。 除去包含在采样/保持抑制电路中的差分放大器的偏移的影响，使得允许高精度的A / D转换。
-
公开(公告)号：US5625308A
公开(公告)日：1997-04-29
申请号：US557556
申请日：1995-11-14
申请人： Osamu Matsumoto , Takahiro Miki , Toshio Kumamoto
发明人： Osamu Matsumoto , Takahiro Miki , Toshio Kumamoto
IPC分类号： H03M1/34 , H03K3/0233 , H03K3/356 , H03K3/289
CPC分类号： H03K3/35606 , H03K3/356034 , H03K3/35613
摘要： A high-performance differential latch circuit which includes a differential amplifier circuit comprised of an NMOS transistor (27) serving as a constant current source, PMOS transistors (3, 4) and NMOS transistors (23,24), a latch circuit comprised of NMOS transistors (25, 26), and a switch circuit comprised of NMOS transistors (21,22,28) for alternately operating the differential amplifying function and latch function, the transistor (27) serving as the constant current source having a drain terminal directly connected to the transistors (23,24) and a source terminal directly connected to a ground voltage (2), whereby the differential latch circuit differentially amplifies the signals without the loss of the constant current source function during the differential amplification.
摘要翻译： 一种高性能差分锁存电路，包括由用作恒流源的NMOS晶体管（27），PMOS晶体管（3,4）和NMOS晶体管（23,24）组成的差分放大器电路，由NMOS 晶体管（25,26）以及由NMOS晶体管（21,22,28）组成的用于交替操作差分放大功能和锁存功能的开关电路，用作恒流源的晶体管（27）具有直接连接的漏极端子 到晶体管（23,24）和直接连接到接地电压（2）的源极端子，由此差分锁存电路在差分放大期间不损失恒定电流源功能而差分放大信号。
-
56.发明授权Series-parallel type A-D converter for realizing high speed operation and low power consumption 失效串并联型A-D转换器，实现高速运行和低功耗
公开(公告)号：US5539406A
公开(公告)日：1996-07-23
申请号：US264676
申请日：1994-06-23
申请人： Hiroyuki Kouno , Toshio Kumamoto , Takahiro Miki
发明人： Hiroyuki Kouno , Toshio Kumamoto , Takahiro Miki
CPC分类号： H03M1/146 , H03M1/0682 , H03M1/365 , H03M1/765
摘要： An upper comparator group compares an analog signal with upper reference potentials applied from upper ladder resistance network. A switch group outputs the predetermined intermediate reference potential of the ladder resistance network to an analog subtracting circuit in response to the upper comparison results. The analog subtracting circuit subtracts the intermediate reference potential from the analog signal for producing an input signal for use in the lower side. A lower ladder resistance network outputs lower reference potentials obtained by dividing by resistors constant static intermediate reference potentials of the ladder resistance network applied from a differential amplifying circuit. A lower comparator group compares the lower reference potentials with the input signal for lower comparison. The upper and the lower comparison results are converted into a digital signal by upper and the lower encoders and the adding/subtracting circuit.
摘要翻译： 上比较器组将模拟信号与上梯形电阻网络施加的较高参考电位进行比较。 开关组响应于较高的比较结果将梯形电阻网络的预定中间参考电位输出到模拟减法电路。 模拟减法电路从用于产生用于下侧的输入信号的模拟信号中减去中间参考电位。 下梯形电阻网络通过将电阻除以由差分放大电路施加的梯形电阻网络的恒定静态中间参考电位而得到的较低参考电位。 较低的比较器组将较低的参考电位与输入信号进行比较，用于较低的比较。 上下比较结果由上下编码器和加减电路转换成数字信号。
-
公开(公告)号：US5317312A
公开(公告)日：1994-05-31
申请号：US990488
申请日：1992-12-14
申请人： Hiroyuki Kouno , Minobu Yazawa , Toshio Kumamoto
发明人： Hiroyuki Kouno , Minobu Yazawa , Toshio Kumamoto
CPC分类号： H03M1/365
摘要： An A/D converter main body is formed in the form of an annulus with a wiring region set as its center, and a ladder resistor array for dividing an input reference voltage and an analog signal line for applying an input analog signal to each comparator in the A/D converter are formed in the form of an annulus with the wiring region set as a center. Wirings from terminals are once concentrated into the wiring region by an input/output line group and then distributed therefrom to circuit elements. Since the ladder resistor array is formed in a circular form, resistance values are less liable to change as compared to the case where the ladder resistor array is bent, resulting in a higher precision of reference voltages for comparison. Further, wiring lengths for control signals to be applied to the circuit elements are made equal, and there is no fear of line delays in the control signals.
摘要翻译： A / D转换器主体形成为以布线区域为中心的环形的形式，以及用于分割输入参考电压的梯形电阻阵列和用于将输入的模拟信号施加到每个比较器的模拟信号线 A / D转换器形成为以布线区域为中心的环形的形式。 来自端子的布线一旦通过输入/输出线组集中到布线区域中，然后从电缆元件分布。 由于梯形电阻器阵列形成为圆形形式，所以与梯形电阻器阵列弯曲的情况相比，电阻值不易变化，因此比较了较高的基准电压精度。 此外，使施加到电路元件的控制信号的布线长度相等，并且不必担心控制信号中的线路延迟。
-
公开(公告)号：US4827262A
公开(公告)日：1989-05-02
申请号：US76858
申请日：1987-07-23
申请人： Toshio Kumamoto , Masao Nakaya
发明人： Toshio Kumamoto , Masao Nakaya
CPC分类号： H03M1/361
摘要： A comparator bank of an A/D converter comprising a plurality of comparators arranged into rows in a folded-back shape and a supply voltage line and a ground line in parallel with each other and connected to the comparators to provide reference potentials thereto according to a distribution shape which rises and falls continuously along the rows of the comparators whereby the linearity of the A/D converter is effectively maintained. The nodes of the comparators do not intersect and are arranged to successively become further from reference points set at the terminals of the supply voltage and ground lines.
摘要翻译： 一种A / D转换器的比较器组，包括多个比较器，其布置成折叠形状的行，并且电源电压线和地线彼此并联连接并连接到比较器，以根据 分布形状沿着比较器的行连续地上升和下降，从而有效地保持A / D转换器的线性。 比较器的节点不相交并且被布置成从设置在电源电压和接地线的端子处的参考点依次变得更远。
-
公开(公告)号：US20110012231A1
公开(公告)日：2011-01-20
申请号：US12891214
申请日：2010-09-27
IPC分类号： H01L29/8605
CPC分类号： H01L27/0207 , H01L27/0629 , H01L27/0802 , H01L28/20
摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
摘要翻译： 本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。 有源区靠近电阻元件配置。 这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。
-
60.发明授权Semiconductor device having resistor elements and method for manufacturing the same 有权具有电阻元件的半导体器件及其制造方法公开(公告)号：US07821078B2
公开(公告)日：2010-10-26
申请号：US12007496
申请日：2008-01-11
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L27/0629 , H01L27/0802 , H01L28/20
摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
摘要翻译： 本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。 有源区靠近电阻元件配置。 这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。
-
-
-
-
-
-
-
-
-
搜索结果
73 条记录 (耗时 0.025 秒)