利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

60 条记录 (耗时 0.027 秒)

    Exposure apparatus
    52.
    发明授权
    Exposure apparatus 失效
    曝光装置

    公开(公告)号：US4828392A

    公开(公告)日：1989-05-09

    申请号：US837766

    申请日：1986-03-10

    申请人： Noboru Nomura ,  Kazuhiro Yamashita ,  Takayoshi Matsumura ,  Midori Yamaguchi

    发明人： Noboru Nomura ,  Kazuhiro Yamashita ,  Takayoshi Matsumura ,  Midori Yamaguchi

    IPC分类号： G03F9/00

    CPC分类号： G03F9/7049 ,  G03F9/7076

    摘要： A reduction projection type alignment and exposure apparatus which comprises a light source, a reticle having a first grating, first lens system, a spatial filter disposed around a Fourier spectral plane of the first lens system, second lens system, a substrate having a second grating, and a plurality of photo-detectors for detecting light intensities of a plurality of spectrums appearing on the spatial filter.The light beam generated from the light source is applied to the reticle at which it is divided into a plurality of diffracted light beams by the first grating, and the diffracted light beams are applied through the first lens system, the spatial filter and the second lens system onto the substrate so that the diffracted light beams are re-diffracted by the second grating, and the re-diffracted light beams appear as a plurality of spectrums on the spatial filter. These spectrums are detected by photo-detectors and used for alignment of the reticle and the substrate.

    摘要翻译： 一种还原投影型取向曝光装置，包括光源，具有第一光栅的掩模版，第一透镜系统，设置在第一透镜系统的傅立叶光谱平面附近的空间滤光器，第二透镜系统，具有第二光栅的基板 以及用于检测出现在空间滤波器上的多个光谱的光强度的多个光检测器。 从光源产生的光束被施加到光掩模，在该掩模版处，由第一光栅将其分成多个衍射光束，衍射光束通过第一透镜系统，空间滤光器和第二透镜 系统到基板上，使得衍射光束被第二光栅重衍射，并且再衍射光束在空间滤光器上表现为多个光谱。 这些光谱由光电检测器检测并用于对准标线片和基板。

    RFID tag manufacturing methods and RFID tags
    54.
    发明授权
    RFID tag manufacturing methods and RFID tags 失效
    RFID标签制造方法和RFID标签

    公开(公告)号：US07936273B2

    公开(公告)日：2011-05-03

    申请号：US11606328

    申请日：2006-11-30

    申请人： Hiroshi Kobayashi ,  Naoki Ishikawa ,  Takayoshi Matsumura

    发明人： Hiroshi Kobayashi ,  Naoki Ishikawa ,  Takayoshi Matsumura

    IPC分类号： G08B13/14 ,  H01Q7/00 ,  H01Q1/40

    CPC分类号： G06K19/07749 ,  G06K19/07752 ,  H01L2224/16 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2224/0401

    摘要： A method includes a step of preparing a strap having a connecting metal pattern formed on a base, and mounted with the circuit chip, the pattern connecting a circuit chip to a metal antenna pattern. A substrate has a concave section which houses the circuit chip and is formed on a first face. The metal antenna pattern extends over a first face and a second face of the base so as to circle them except for the concave section and to have the both ends positioned across the concave section. The method includes a connection step of positioning and directing the strap and the substrate to house the circuit chip in the concave section and covering the strap and the substrate with a covering material so as to fix the strap and the substrate in a state where the connection metal pattern is connected to the metal antenna pattern.

    摘要翻译： 一种方法包括制备具有形成在基底上的连接金属图案并且安装有电路芯片的带的步骤，该图案将电路芯片连接到金属天线图案。 基板具有容纳电路芯片并形成在第一面上的凹部。 金属天线图案在基座的第一面和第二面之上延伸，以便除了凹部之外使其圆形，并且使两端位于凹部的两端。 该方法包括一个连接步骤，用于定位和引导带子和基底，以将电路芯片容纳在凹形部分中，并用覆盖材料覆盖带子和基底，从而将带子和基底固定在连接 金属图案连接到金属天线图案。

    Bonding apparatus and method of bonding for a semiconductor chip
    56.
    发明授权
    Bonding apparatus and method of bonding for a semiconductor chip 失效
    用于半导体芯片的接合装置和接合方法

    公开(公告)号：US07432129B2

    公开(公告)日：2008-10-07

    申请号：US10991851

    申请日：2004-11-19

    申请人： Takayoshi Matsumura

    发明人： Takayoshi Matsumura

    IPC分类号： H01L21/44

    CPC分类号： H01L24/81 ,  B23K20/10 ,  B23K2101/40 ,  H01L24/75 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01079

    摘要： A method of bonding and a bonding apparatus for a semiconductor chip that apply ultrasonic vibration to the semiconductor chip to bond the semiconductor chip to a substrate carry out leveling effectively at low cost and in a short time and can improve the bonding between the semiconductor chip and the substrate. In a positioning step, bumps of the semiconductor chip and pads of the substrate are positioned and placed in contact. In a leveling step, ultrasonic vibration of a first predetermined frequency is applied to the semiconductor chip to make the bumps of the semiconductor chip and the pads of a substrate rub against each other to level the bumps. In a bonding step, ultrasonic vibration of a second predetermined frequency that differs to the first predetermined frequency is applied to the semiconductor chip to bond the bumps and pads of the semiconductor chip and the substrate.

    摘要翻译： 一种用于半导体芯片的半导体芯片的接合方法和半导体芯片的接合装置，用于将半导体芯片施加到半导体芯片以将半导体芯片接合到基板上，以低成本和短时间有效地进行调平，并且可以改善半导体芯片和 底物。 在定位步骤中，将半导体芯片和衬底的焊盘定位和放置接触。 在平整步骤中，将第一预定频率的超声波振动施加到半导体芯片，以使半导体芯片的凸块和基板的焊盘相互摩擦以使凸块平坦化。 在接合步骤中，向半导体芯片施加与第一预定频率不同的第二预定频率的超声波振动，以将半导体芯片和基板的凸块和焊盘接合。

    Method of assembling a carriage assembly
    58.
    发明申请
    Method of assembling a carriage assembly 审中-公开
    组装滑架组件的方法

    公开(公告)号：US20070180673A1

    公开(公告)日：2007-08-09

    申请号：US11444292

    申请日：2006-05-31

    申请人： Hiroshi Kobayashi ,  Hidehiko Kira ,  Naoki Ishikawa ,  Takayoshi Matsumura

    发明人： Hiroshi Kobayashi ,  Hidehiko Kira ,  Naoki Ishikawa ,  Takayoshi Matsumura

    IPC分类号： B23P11/00 ,  B21D39/00

    CPC分类号： B23P11/005 ,  B21D39/032 ,  B21J5/006 ,  B21K25/00 ,  Y10T29/49764 ,  Y10T29/49771 ,  Y10T29/49774 ,  Y10T29/49908

    摘要： There is provided a method of assembling a carriage assembly that can crimp suspensions to carriage arms by applying ultrasonic vibration to a crimping tool without causing deformation of the suspensions and the like. The method of assembling a carriage assembly aligns attachment holes provided in front ends of carriage arms and crimping portions provided on suspensions to set the suspensions on the carriage arms and then presses a metal ball through crimping holes provided in the crimping portions while applying ultrasonic vibration to a crimping tool to crimp the suspensions to the carriage arms. The suspensions are crimped to the carriage arms by detecting stress that acts on the crimping tool when the metal ball is pressed in by the crimping tool and controlling the amplitude of the ultrasonic vibration applied to the crimping tool so as to increase and decrease in accordance with the magnitude of the stress.

    摘要翻译： 提供了一种组装滑架组件的方法，其可以通过对压接工具施加超声振动而不会引起悬架等的变形而将悬架压紧到滑架臂。 组装滑架组件的方法将设置在滑架臂的前端的设置孔和设置在悬架上的压接部对准，以将悬架设置在滑架臂上，然后通过设置在压接部中的压接孔将金属球压入同时施加超声波振动 压接工具，以将悬架压紧到托架臂上。 通过检测当金属球被压接工具压入时作用在压接工具上的应力，并且控制施加到压接工具的超声波振动的振幅以按照 压力的大小。

    Method of bonding and bonding apparatus for a semiconductor chip
    59.
    发明授权
    Method of bonding and bonding apparatus for a semiconductor chip 失效
    半导体芯片的接合和接合装置的方法

    公开(公告)号：US07150388B2

    公开(公告)日：2006-12-19

    申请号：US11022867

    申请日：2004-12-28

    申请人： Takayoshi Matsumura

    发明人： Takayoshi Matsumura

    IPC分类号： B23K1/06

    CPC分类号： B23K20/10 ,  B23K2101/40 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/75305 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01079

    摘要： A method of bonding and a bonding apparatus for a semiconductor chip uses ultrasonic vibration but can improve the bonds between electrode terminals of a semiconductor chip and a substrate. In a method of bonding a semiconductor chip that places electrode terminals of the semiconductor chip and electrode terminals of a substrate in contact and applies ultrasonic vibration to the semiconductor chip to bond the electrode terminals of the semiconductor chip and the substrate together, the ultrasonic vibration is compressional waves that are transmitted to the semiconductor chip and is set so that a half-wavelength of the ultrasonic vibration is a length given by multiplying a gap between adjacent electrode terminals in a direction of the compressional waves by a reciprocal of a natural number, and maximum amplitude points are located at positions of the respective electrode terminals of the semiconductor chip and the substrate.

    摘要翻译： 用于半导体芯片的接合方法和接合装置使用超声波振动，但是可以改善半导体芯片的电极端子与基板之间的结合。 在将半导体芯片的电极端子与基板的电极端子接触的半导体芯片接合的方法中，对半导体芯片施加超声波振动，将半导体芯片和基板的电极端子接合在一起，超声波振动为 发送到半导体芯片的压缩波被设定为使得超声波振动的半波长是通过将相邻的电极端子之间的间隙沿着自然数的倒数乘以相邻的电极端子之间的间隔而给出的长度，以及 最大幅度点位于半导体芯片和基板的各个电极端子的位置。

    Aligning exposure method
    60.
    发明授权
    Aligning exposure method 失效
    调整曝光方式

    公开(公告)号：US4636077A

    公开(公告)日：1987-01-13

    申请号：US599734

    申请日：1984-04-12

    申请人： Noboru Nomura ,  Koichi Kugimiya ,  Takayoshi Matsumura ,  Taketoshi Yonezawa

    发明人： Noboru Nomura ,  Koichi Kugimiya ,  Takayoshi Matsumura ,  Taketoshi Yonezawa

    IPC分类号： G03F7/20 ,  G03F9/00 ,  G01B9/02

    CPC分类号： G03F9/7049 ,  G03F7/70408 ,  G03F9/7076

    摘要： Disclosed in an aligning and exposing method suitable for use in the production of LSIs. Coherent ray beams are applied from two directions to form interference fringe through interference of the coherent rays. A diffraction grid is disposed in the optic paths of the ray beams substantially in parallel with the interference fringe. The ray beams reflected and transmitted by the grid are converged by a lens system and the intensities of the ray beams are measured to detect the relative position between the interference fringe formed by two coherent ray beams and the diffraction grid, thereby to permit a highly accurate alignment of fine semiconductor element. The pitch of the grid on the substrate is selected to be n (n being an integer) times as large as the pitch of the interference fringe, so that the grid for alignment purpose is formed simultaneously with the formation of the LSI pattern by photolithographic technic. With this method, it is possible to attain a high degree of accuracy of alignment, and to conduct the subsequent exposure using the same ray beam source as that used for the alignment.

    摘要翻译： 公开了适用于制造LSI的对准和曝光方法。 从两个方向施加相干射线束，以形成干涉条纹通过相干射线的干涉。 衍射栅格设置在基本上与干涉条纹平行的射线束的光路中。 由栅格反射和透射的光束由透镜系统会聚，并且测量射线束的强度以检测由两个相干射线束和衍射栅格形成的干涉条纹之间的相对位置，从而允许高精度 精细半导体元件的对准。 衬底上的栅格的间距选择为干涉条纹的间距的n（n是整数）倍，使得用于对准目的的栅格与通过光刻技术形成LSI图案同时形成 。 利用该方法，可以获得高精度的对准，并且可以使用与用于对准的相同的光束源进行后续曝光。