公开(公告)号：US20050082637A1

公开(公告)日：2005-04-21

申请号：US10964703

申请日：2004-10-15

申请人： Takumi Mikawa ,  Eiji Fujii

发明人： Takumi Mikawa ,  Eiji Fujii

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L21/8242 ,  H01L29/00

CPC分类号： H01L28/55 ,  H01L21/7687 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75 ,  H01L28/91

摘要： A semiconductor device is provided with an insulating film which is formed on a semiconductor substrate and has a first recess, a capacitor lower electrode which is formed on the walls and the bottom of the first recess and has a second recess, and a capacitor insulating film which is formed on the walls and the bottom of the second recess and has a third recess, and a capacitor upper electrode embedded in the third recess.

摘要翻译： 半导体器件设置有绝缘膜，该绝缘膜形成在半导体衬底上并且具有第一凹部，形成在第一凹部的壁和底部上并具有第二凹部的电容器下电极，以及电容器绝缘膜 其形成在第二凹部的壁和底部上，并且具有第三凹部，以及嵌入在第三凹部中的电容器上电极。

公开(公告)号：US20050041505A1

公开(公告)日：2005-02-24

申请号：US10957618

申请日：2004-10-05

申请人： Takumi Mikawa

发明人： Takumi Mikawa

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  G11C7/00

CPC分类号： H01L27/11509 ,  H01L21/28568 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

摘要： A capacitor upper electrode and a wiring are electrically connected to each other by using a plug and a conductive layer formed below a capacitive element without using a plug that directly connects the capacitor upper electrode to the wiring provided thereon via an interlayer insulating film therebetween. Alternatively, the capacitor upper electrode is covered by a conductive hydrogen barrier film, and the capacitor upper electrode and the wiring are electrically connected to each other via both a plug connecting the wiring and the conductive hydrogen barrier film to each other and the conductive hydrogen barrier film.

公开(公告)号：US06753566B2

公开(公告)日：2004-06-22

申请号：US10441118

申请日：2003-05-20

申请人： Toshie Kutsunai ,  Shinichiro Hayashi ,  Takumi Mikawa ,  Yuji Judai

发明人： Toshie Kutsunai ,  Shinichiro Hayashi ,  Takumi Mikawa ,  Yuji Judai

IPC分类号： H01L27108

CPC分类号： H01L28/55

摘要： An impurity diffusion layer serving as the source or the drain of a transistor is formed in a semiconductor substrate, and a protection insulating film is formed so as to cover the transistor. A capacitor lower electrode, a capacitor dielectric film of an oxide dielectric film and a capacitor upper electrode are successively formed on the protection insulating film. A plug for electrically connecting the impurity diffusion layer of the transistor to the capacitor lower electrode is buried in the protection insulating film. An oxygen barrier layer is formed between the plug and the capacitor lower electrode. The oxygen barrier layer is made from a composite nitride that is a mixture or an alloy of a first nitride having a conducting property and a second nitride having an insulating property.

摘要翻译： 在半导体衬底中形成用作晶体管的源极或漏极的杂质扩散层，形成覆盖晶体管的保护绝缘膜。 在保护绝缘膜上依次形成电容器下电极，氧化物电介质膜的电容电介质膜和电容器上电极。 用于将晶体管的杂质扩散层电连接到电容器下电极的插头埋入保护绝缘膜中。 在塞子和电容器下电极之间形成氧阻隔层。 氧阻隔层由作为具有导电性的第一氮化物和具有绝缘性的第二氮化物的混合物或合金的复合氮化物制成。

公开(公告)号：US06750492B2

公开(公告)日：2004-06-15

申请号：US10053693

申请日：2002-01-24

申请人： Takumi Mikawa ,  Toshie Kutsunai ,  Yuji Judai

发明人： Takumi Mikawa ,  Toshie Kutsunai ,  Yuji Judai

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L27/10894 ,  H01L27/11507 ,  H01L28/55

摘要： A semiconductor memory device of the present invention includes: a semiconductor substrate; a memory cell capacitor for storing data, including a first electrode provided above the semiconductor substrate, a capacitance insulating film formed on the first electrode, and a second electrode provided on the capacitance insulating film; a step reducing film covering an upper surface and a side surface of the memory cell capacitor; and an overlying hydrogen barrier film covering the step reducing film.

摘要翻译： 本发明的半导体存储器件包括：半导体衬底; 用于存储数据的存储单元电容器，包括设置在半导体衬底上的第一电极，形成在第一电极上的电容绝缘膜和设置在电容绝缘膜上的第二电极; 覆盖所述存储单元电容器的上表面和侧面的阶梯降低膜; 以及覆盖降低层的覆盖氢阻挡膜。

公开(公告)号：US09184381B2

公开(公告)日：2015-11-10

申请号：US13810800

申请日：2011-10-06

申请人： Takumi Mikawa ,  Yukio Hayakawa ,  Takeki Ninomiya ,  Yoshio Kawashima ,  Shinichi Yoneda

发明人： Takumi Mikawa ,  Yukio Hayakawa ,  Takeki Ninomiya ,  Yoshio Kawashima ,  Shinichi Yoneda

IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L27/10

CPC分类号： H01L45/145 ,  H01L27/101 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1625

摘要： A variable resistance nonvolatile storage element includes: a first electrode; a second electrode; and a variable resistance layer having a resistance value that reversibly changes based on an electrical signal applied between the electrodes, wherein the variable resistance layer has a structure formed by stacking a first transition metal oxide layer, a second transition metal oxide layer, and a third transition metal oxide layer in this order, the first transition metal oxide layer having a composition expressed as MOx (where M is a transition metal and O is oxygen), the second transition metal oxide layer having a composition expressed as MOy (where x>y), and the third transition metal oxide layer having a composition expressed as MOz (where y>z).

摘要翻译： 可变电阻非易失性存储元件包括：第一电极; 第二电极; 以及可变电阻层，其具有基于施加在所述电极之间的电信号而可逆地变化的电阻值，其中所述可变电阻层具有通过堆叠第一过渡金属氧化物层，第二过渡金属氧化物层和第三过渡金属氧化物层而形成的结构 过渡金属氧化物层，第一过渡金属氧化物层具有以MOx表示的组成（其中M是过渡金属，O是氧），第二过渡金属氧化物层具有以MOy表示的组成（其中x> y ）和具有表示为MOz（其中y> z）的组成的第三过渡金属氧化物层。

公开(公告)号：US08889478B2

公开(公告)日：2014-11-18

申请号：US13637465

申请日：2011-11-18

申请人： Takumi Mikawa ,  Yukio Hayakawa ,  Yoshio Kawashima ,  Takeki Ninomiya

发明人： Takumi Mikawa ,  Yukio Hayakawa ,  Yoshio Kawashima ,  Takeki Ninomiya

IPC分类号： H01L45/00 ,  H01L21/8239 ,  H01L21/02 ,  H01L27/24 ,  H01L27/102

CPC分类号： H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1675

摘要： Provided is a method for manufacturing a variable resistance nonvolatile semiconductor memory element, and a nonvolatile semiconductor memory element which make it possible to operate at a low voltage and high speed when initial breakdown is caused, and exhibit favorable diode element characteristics. The method for manufacturing the nonvolatile semiconductor memory element includes, after forming a top electrode of a variable resistance element and at least before forming a top electrode of an MSM diode element, oxidizing to insulate a portion of a variable resistance film in a region around an end face of a variable resistance layer.

摘要翻译： 提供一种用于制造可变电阻非易失性半导体存储元件的方法，以及使得可以在初始击穿时以低电压和高速操作的可变电阻非易失性半导体存储元件，并且表现出良好的二极管元件特性。 制造非易失性半导体存储元件的方法包括：在形成可变电阻元件的顶部电极之后，并且至少在形成MSM二极管元件的顶部电极之前，氧化以使可变电阻膜的一部分在一个周围的区域中绝缘 可变电阻层的端面。

公开(公告)号：US08871561B2

公开(公告)日：2014-10-28

申请号：US13805233

申请日：2012-01-30

申请人： Ichirou Takahashi ,  Takumi Mikawa

发明人： Ichirou Takahashi ,  Takumi Mikawa

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1683 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1625

摘要： Provided is a method for manufacturing a variable resistance nonvolatile storage device, which prevents electrical conduction between lower electrodes and upper electrodes of variable resistance elements in the memory cell holes. The method includes: forming lower copper lines; forming a third interlayer insulating layer; forming memory cell holes in the third interlayer insulating layer, an opening diameter of upper portions of the memory cell holes being smaller than bottom portions; forming a metal electrode layer on the bottom of each memory cell holes by sputtering; embedding and forming a variable resistance layer in each memory cell hole; and forming upper copper lines connected to the variable resistance layer embedded and formed in each memory cell hole.

摘要翻译： 提供一种制造可变电阻非易失性存储装置的方法，其防止存储单元孔中的下电极和可变电阻元件的上电极之间的导电。 该方法包括：形成较低的铜线; 形成第三层间绝缘层; 在第三层间绝缘层中形成存储单元孔，存储单元孔的上部的开口直径小于底部; 通过溅射在每个存储单元孔的底部形成金属电极层; 在每个存储单元孔中嵌入并形成可变电阻层; 并且形成连接到嵌入并形成在每个存储单元孔中的可变电阻层的上铜线。

公开(公告)号：US08861257B2

公开(公告)日：2014-10-14

申请号：US13634700

申请日：2011-11-24

申请人： Yukio Hayakawa ,  Takumi Mikawa ,  Takeki Ninomiya

发明人： Yukio Hayakawa ,  Takumi Mikawa ,  Takeki Ninomiya

IPC分类号： G11C11/00 ,  H01L27/10 ,  H01L45/00 ,  H01L27/02 ,  H01L27/24 ,  G11C13/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/55 ,  H01L27/02 ,  H01L27/2427 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A nonvolatile memory element includes a variable resistance layer located between a lower electrode and an upper electrode and having a resistance value that reversibly changes based on electrical signals applied between these electrodes. The variable resistance layer includes at least two layers: a first variable resistance layer including a first transition metal oxide; and a second variable resistance layer including a second transition metal oxide and a transition metal compound. The second transition metal oxide has an oxygen content atomic percentage lower than an oxygen content atomic percentage of the first transition metal oxide, the transition metal compound contains either oxygen and nitrogen or oxygen and fluorine, and the second transition metal oxide and the transition metal compound are in contact with the first variable resistance layer.

摘要翻译： 非易失性存储元件包括位于下电极和上电极之间的可变电阻层，并且具有基于施加在这些电极之间的电信号而可逆地改变的电阻值。 可变电阻层包括至少两层：包含第一过渡金属氧化物的第一可变电阻层; 以及包含第二过渡金属氧化物和过渡金属化合物的第二可变电阻层。 第二过渡金属氧化物的氧含量原子百分比低于第一过渡金属氧化物的氧含量原子百分比，过渡金属化合物含有氧和氮或氧和氟，第二过渡金属氧化物和过渡金属化合物 与第一可变电阻层接触。

公开(公告)号：US20140098595A1

公开(公告)日：2014-04-10

申请号：US14122708

申请日：2013-03-27

申请人： Yoshio Kawashima ,  Yukio Hayakawa ,  Takumi Mikawa

发明人： Yoshio Kawashima ,  Yukio Hayakawa ,  Takumi Mikawa

IPC分类号： H01L45/00 ,  G11C13/00

CPC分类号： H01L45/12 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

摘要： A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a first variable resistance element and a first current steering element and a parameter generation circuit including a reference cell including a second variable resistance element and a second current steering element having the same current density-voltage characteristic as that of the first current steering element, wherein a conductive shorting layer for causing short-circuiting between the electrodes is formed on the side surfaces of the second variable resistance element.

摘要翻译： 一种非易失性存储器件包括：存储单元阵列，包括多个存储单元，每个存储单元包括第一可变电阻元件和第一电流导引元件;以及参数产生电路，其包括具有第二可变电阻元件和第二电流元件 所述转向元件具有与所述第一电流操舵元件相同的电流密度 - 电压特性，其中在所述第二可变电阻元件的侧表面上形成用于在所述电极之间引起短路的导电短路层。

公开(公告)号：US08692222B2

公开(公告)日：2014-04-08

申请号：US13575338

申请日：2011-12-12

申请人： Shinichi Yoneda ,  Takumi Mikawa

发明人： Shinichi Yoneda ,  Takumi Mikawa

IPC分类号： H01L47/00

CPC分类号： H01L45/146 ,  G11C13/0007 ,  G11C2213/72 ,  H01L45/1233

摘要： A nonvolatile memory element according to the present disclosure includes: a variable resistance element including a first electrode layer, a second electrode layer, and a variable resistance layer which is located between the first electrode layer and the second electrode layer and has a resistance value that reversibly changes based on an electrical signal applied between the first electrode layer and the second electrode layer; and a fixed resistance layer having a predetermined resistance value and stacked together with the variable resistance element. The variable resistance layer includes (i) a first transition metal oxide layer which is oxygen deficient and (ii) a second transition metal oxide layer which has a higher oxygen content atomic percentage than the first transition metal oxide layer. The predetermined resistance value ranges from 70Ω to 1000Ω inclusive.

摘要翻译： 根据本公开的非易失性存储元件包括：可变电阻元件，包括位于第一电极层和第二电极层之间的第一电极层，第二电极层和可变电阻层，并且具有电阻值， 基于施加在第一电极层和第二电极层之间的电信号可逆地改变; 以及具有预定电阻值并与可变电阻元件一起堆叠的固定电阻层。 可变电阻层包括（i）缺氧的第一过渡金属氧化物层和（ii）具有比第一过渡金属氧化物层更高的氧含量原子百分比的第二过渡金属氧化物层。 预定电阻值范围为70＆OHgr; 至1000＆OHgr; 包括的。