公开(公告)号：US07898049B2

公开(公告)日：2011-03-01

申请号：US11378020

申请日：2006-03-17

申请人： John E. Dillon ,  Timothy J. Hoague ,  Robert K. Leidy

发明人： John E. Dillon ,  Timothy J. Hoague ,  Robert K. Leidy

IPC分类号： H01L31/0232

CPC分类号： H01L27/14685 ,  H01L27/14627 ,  H01L31/02327

摘要： A structure and method for increasing the sensitivity of pixel sensors by eliminating a gap space formed between adjacent microlens structures in a pixel sensor array. Advantageously, exposure and flowing conditions are such that adjacent microlens structures touch (are webbed) at a horizontal cross-section, yet have a round lens shape in all directions. Particularly, exposure and flowing conditions are such that each touching microlens structure is formed to have a matched uniform radius of curvature at a horizontal cross-section and at a 45 degree cross-sections. To improve quality of mircrolens structure uniformity exhibited at all pixel locations including those near a pixel array edge or corner, a top anti-reflective coating layer is applied on top of a photoresist layer prior to the exposure and flowing steps.

摘要翻译： 通过消除在像素传感器阵列中相邻的微透镜结构之间形成的间隙空间来增加像素传感器的灵敏度的结构和方法。 有利地，曝光和流动条件使得相邻的微透镜结构以水平横截面接触（被蹼状），但在所有方向上具有圆形透镜形状。 特别地，曝光和流动条件使得每个触摸的微透镜结构形成为在水平横截面和45度横截面处具有匹配的均匀的曲率半径。 为了提高在包括像素阵列边缘或角落附近的像素位置的所有像素位置处显示的微电极结构均匀性的质量，在曝光和流动步骤之前，将顶部抗反射涂层施加在光致抗蚀剂层的顶部。

公开(公告)号：US07829965B2

公开(公告)日：2010-11-09

申请号：US10908601

申请日：2005-05-18

申请人： Timothy J. Hoague ,  Robert K. Leidy

发明人： Timothy J. Hoague ,  Robert K. Leidy

IPC分类号： H01L31/0232 ,  G03F7/20

CPC分类号： H01L27/14685 ,  H01L27/14627 ,  H01L31/02327

摘要： A structure and method for increasing the sensitivity of pixel sensors by eliminating a gap space formed between adjacent microlens structures in a pixel sensor array. Advantageously, exposure and flowing conditions are such that adjacent microlens structures touch (are webbed) at a horizontal cross-section, yet have a round lens shape in all directions. Particularly, exposure and flowing conditions are such that each touching microlens structure is formed to have a matched uniform radius of curvature at a horizontal cross-section and at a 45 degree cross-sections.

摘要翻译： 通过消除在像素传感器阵列中相邻的微透镜结构之间形成的间隙空间来增加像素传感器的灵敏度的结构和方法。 有利地，曝光和流动条件使得相邻的微透镜结构以水平横截面接触（被蹼状），但在所有方向上具有圆形透镜形状。 特别地，曝光和流动条件使得每个触摸的微透镜结构形成为在水平横截面和45度横截面处具有匹配的均匀的曲率半径。

公开(公告)号：US07687210B2

公开(公告)日：2010-03-30

申请号：US11767633

申请日：2007-06-25

申请人： Robert K. Leidy ,  Paul D. Sonntag ,  Peter J. Sullivan

发明人： Robert K. Leidy ,  Paul D. Sonntag ,  Peter J. Sullivan

IPC分类号： G03F9/00 ,  G03C5/00

CPC分类号： G03F7/70475 ,  G03F7/70466 ,  Y10S430/143

摘要： A method for manufacturing a stitched space in a semiconductor circuit implements a photolithographic process for printing one or more image fields on a wafer surface, each image field corresponding to a portion of a circuit or device and including a space that is to be stitched in adjacent image fields. The space to be stitched that is produced from an image field is overlapped onto the space to be stitched produced from the adjacent image field, however, the overlapped space from the adjacent image fields is intentionally misaligned. The stitched space is then subject to the double light exposure dose to print the stitched space, with the result that an overlay tolerance of the stitched space is improved.

摘要翻译： 用于制造半导体电路中的缝合空间的方法实现了用于在晶片表面上印刷一个或多个图像场的光刻工艺，每个图像场对应于电路或器件的一部分，并且包括将被相邻的缝合空间 图像字段。 从图像场产生的要缝制的空间被重叠在从相邻图像场产生的待缝合的空间上，然而，与相邻图像场的重叠空间被有意地对准。 然后缝合的空间经受双倍曝光剂量以打印缝合空间，结果是改善了缝合空间的覆盖公差。

公开(公告)号：US20080113456A1

公开(公告)日：2008-05-15

申请号：US11559983

申请日：2006-11-15

申请人： Steven R. Codding ,  Timothy C. Krywanczyk ,  Robert K. Leidy

发明人： Steven R. Codding ,  Timothy C. Krywanczyk ,  Robert K. Leidy

IPC分类号： H01L31/18

CPC分类号： H01L31/18 ,  H01L21/67132 ,  H01L27/14618 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for protecting a semiconductor wafer fabricated for image sensing operation from contamination and/or physical damage to a front wafer surface during post-fabrication processing. The method includes applying a protective tape layer on the front surface of the semiconductor wafer in order to protect active light sensors fabricated thereon.

摘要翻译： 一种用于在制造后处理期间保护用于图像感测操作制造的半导体晶片免受污染和/或对前晶片表面的物理损伤的方法。 该方法包括在半导体晶片的前表面上施加保护带层，以保护在其上制造的有源光传感器。

公开(公告)号：US06716559B2

公开(公告)日：2004-04-06

申请号：US10016211

申请日：2001-12-13

申请人： Robert K. Leidy ,  Timothy C. Milmore ,  Matthew C. Nicholls

发明人： Robert K. Leidy ,  Timothy C. Milmore ,  Matthew C. Nicholls

IPC分类号： G03F900

CPC分类号： G03F7/70633 ,  Y10S438/975

摘要： A method and system for determining overlay tolerances. The method comprises the steps of exposing wafers at different critical dimensions (preferably, above, below, and at optimum image size); and varying the overlay across each wafer, preferably by intentionally increasing the magnification. Functional yield data are used to determine the overlay tolerance for each of the image sizes. The present invention, thus, studies the interaction of image size and feature misalignment. Prior to this invention, the only way to attain this information was to process a large number of lots and create a trend of image size and alignment vs. yield. The present invention solves the problem by determining the overlay tolerance based on yield data from a single lot. The design can then be altered or the overlay limit can be tightened (or relaxed) based on failure analysis of the regions/features that are most sensitive to misalignment.

摘要翻译： 一种用于确定覆盖公差的方法和系统。 该方法包括以不同临界尺寸（优选高于，低于，最佳图像尺寸）曝光晶片的步骤; 并且优选地通过有意地增加放大倍数来改变跨每个晶片的覆盖层。 功能产量数据用于确定每个图像尺寸的覆盖公差。 因此，本发明研究图像尺寸和特征不对准的相互作用。 在本发明之前，获得这些信息的唯一方法是处理大量的批次，并产生图像尺寸和对准与产量的趋势。 本发明通过基于来自单个批次的产量数据确定覆盖公差来解决该问题。 然后可以基于对未对准最敏感的区域/特征的故障分析，改变设计或覆盖限制（或放松）。

公开(公告)号：US06620635B2

公开(公告)日：2003-09-16

申请号：US10079092

申请日：2002-02-20

申请人： Robert K. Leidy

发明人： Robert K. Leidy

IPC分类号： H01L2166

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator is provided. The linewidth measurement structure including: a damascene polysilicon line formed in the insulator, the polysilicon line having an doped region having a predetermined resistivity.

公开(公告)号：US06184151B2

公开(公告)日：2001-02-06

申请号：US09275541

申请日：1999-03-24

申请人： William J. Adair ,  Richard A. Ferguson ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  William Hsioh-Lien Ma ,  Ronald M. Martino ,  Song Peng

发明人： William J. Adair ,  Richard A. Ferguson ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  William Hsioh-Lien Ma ,  Ronald M. Martino ,  Song Peng

IPC分类号： H01L21461

CPC分类号： H01L27/10864 ,  H01L21/0332 ,  H01L21/0334 ,  Y10S438/942

摘要： A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.

摘要翻译： 公开了一种在光刻工艺中形成正方形形状图像的方法，其中沿第一方向延伸的第一多条线被限定在第一，通常是牺牲层中，然后定义第二抗蚀剂，其中线以相交图案 到第一层的那些，从而在第一和第二层交叉的任何地方以及在线之间的开放区域中产生拐角图像。 提出了用于显影方形交叉区域和由开口限定的方角区域的方法。 此外，公开了一种光掩模，其中使用双曝光工艺独立地对角形图像的长度和宽度进行图案化。

公开(公告)号：US5981148A

公开(公告)日：1999-11-09

申请号：US895749

申请日：1997-07-17

申请人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  Cuc K. Huynh ,  Robert K. Leidy ,  Paul W. Pastel

发明人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  Cuc K. Huynh ,  Robert K. Leidy ,  Paul W. Pastel

IPC分类号： H01L29/78 ,  G03F7/095 ,  G03F7/38 ,  H01L21/027 ,  H01L21/265 ,  H01L21/311 ,  H01L21/336 ,  G03C5/56 ,  H01L21/71

CPC分类号： H01L29/66492 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/6659 ,  G03F7/095 ,  H01L21/26586

摘要： The preferred embodiment of the present invention overcomes the disadvantages of the prior art by using hybrid resist to define a sidewall spacer region and form a new type of sidewall spacer. The preferred method allows for more controlled doping at the gate-source and gate-drain junctions by defining sidewall spacer troughs using hybrid resist. Implants can then be made through the troughs to precisely control the doping at the gate junctions. Additionally, sidewall spacers can then be formed in the sidewall spacer troughs. The dimensions of the sidewall spacers is determined by the hybrid resist and can thus be made smaller than traditional resist processes. Additionally, forming the sidewall spacers using hybrid resist allows for their width to be determined independent of the depth of the gate material.

公开(公告)号：US09054671B2

公开(公告)日：2015-06-09

申请号：US13292729

申请日：2011-11-09

申请人： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

发明人： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

IPC分类号： H03H9/00 ,  H03H9/17 ,  H03H9/56 ,  H03H9/05 ,  H01L41/00 ,  H03H9/02

CPC分类号： H03H9/545 ,  H03H9/0547 ,  H03H9/171 ,  H03H9/173 ,  H03H9/56 ,  H03H2009/02204 ,  Y10T29/42

摘要： Tunable filter structures, methods of manufacture and design structures are disclosed. The method of forming a filter structure includes forming a piezoelectric resonance filter over a cavity structure. The forming of the piezoelectric resonance filter includes: forming an upper electrode on one side of a piezoelectric material; and forming a lower electrode on an opposing side of the piezoelectric material. The method further includes forming a micro-electro-mechanical structure (MEMS) cantilever beam at a location in which, upon actuation, makes contact with the piezoelectric resonance filter.

摘要翻译： 公开了可调谐滤波器结构，制造方法和设计结构。 形成滤波器结构的方法包括在空腔结构上形成压电谐振滤波器。 压电谐振滤波器的形成包括：在压电材料的一侧上形成上电极; 以及在所述压电材料的相对侧上形成下电极。 该方法还包括在致动时与压电谐振滤波器接触的位置处形成微机电结构（MEMS）悬臂梁。

公开(公告)号：US20130119434A1

公开(公告)日：2013-05-16

申请号：US13296496

申请日：2011-11-15

申请人： JAMES W. ADKISSON ,  David L. Harame ,  Robert K. Leidy ,  Qizhi Liu

发明人： JAMES W. ADKISSON ,  David L. Harame ,  Robert K. Leidy ,  Qizhi Liu

IPC分类号： H01L29/737 ,  H01L29/73 ,  H01L21/331

CPC分类号： H01L29/732 ,  H01L29/7371

摘要： Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.

摘要翻译： 公开了晶体管（例如双极结型晶体管（BJT）或异质结双极晶体管（HBT））的实施例以及形成具有集电极区域的晶体管的方法，该集电极区域具有用于还原的基极 - 集电极结电容Cbc的受保护的上边缘部分。 在实施例中，集电极区域位于衬底内侧向与沟槽隔离区域相邻的位置。 掩模层覆盖沟槽隔离区域并且进一步横向延伸到收集器区域的边缘部分上。 本征基极层的第一部分位于集电极区域的中心部分的上方，并且本征基极层的第二部分位于掩模层之上。 在处理期间，这些掩模层防止在隔离区域 - 集电极区界面处的沟槽隔离区的上角部形成裂缝，并且进一步限制从随后形成的凸起的外在基极层到集电极区域的掺杂剂扩散。