公开(公告)号：US06184151B2

公开(公告)日：2001-02-06

申请号：US09275541

申请日：1999-03-24

申请人： William J. Adair ,  Richard A. Ferguson ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  William Hsioh-Lien Ma ,  Ronald M. Martino ,  Song Peng

发明人： William J. Adair ,  Richard A. Ferguson ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  William Hsioh-Lien Ma ,  Ronald M. Martino ,  Song Peng

IPC分类号： H01L21461

CPC分类号： H01L27/10864 ,  H01L21/0332 ,  H01L21/0334 ,  Y10S438/942

摘要： A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.

摘要翻译： 公开了一种在光刻工艺中形成正方形形状图像的方法，其中沿第一方向延伸的第一多条线被限定在第一，通常是牺牲层中，然后定义第二抗蚀剂，其中线以相交图案 到第一层的那些，从而在第一和第二层交叉的任何地方以及在线之间的开放区域中产生拐角图像。 提出了用于显影方形交叉区域和由开口限定的方角区域的方法。 此外，公开了一种光掩模，其中使用双曝光工艺独立地对角形图像的长度和宽度进行图案化。

公开(公告)号：US5959325A

公开(公告)日：1999-09-28

申请号：US917009

申请日：1997-08-21

申请人： William J. Adair ,  Richard A. Ferguson ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  William Hsioh-Lien Ma ,  Ronald M. Martino ,  Song Peng

发明人： William J. Adair ,  Richard A. Ferguson ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  William Hsioh-Lien Ma ,  Ronald M. Martino ,  Song Peng

IPC分类号： H01L21/033 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L21/0332 ,  H01L21/0334 ,  Y10S438/942

摘要： A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.

摘要翻译： 公开了一种在光刻工艺中形成正方形形状图像的方法，其中沿第一方向延伸的第一多条线被限定在第一，通常是牺牲层中，然后定义第二抗蚀剂，其中线以相交图案 到第一层的那些，从而在第一和第二层交叉的任何地方以及在线之间的开放区域中产生拐角图像。 提出了用于显影方形交叉区域和由开口限定的方角区域的方法。 此外，公开了一种光掩模，其中使用双曝光工艺独立地对角形图像的长度和宽度进行图案化。

公开(公告)号：US06358813B1

公开(公告)日：2002-03-19

申请号：US09713766

申请日：2000-11-15

申请人： Steven J. Holmes ,  Charles Black ,  David J. Frank ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  William Hsioh-Lien Ma ,  Keith R. Milkove ,  Kathryn W. Guarini

发明人： Steven J. Holmes ,  Charles Black ,  David J. Frank ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  William Hsioh-Lien Ma ,  Keith R. Milkove ,  Kathryn W. Guarini

IPC分类号： H01L2120

CPC分类号： H01L28/92

摘要： Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

摘要翻译： 描述了通过在半导体介质上提供第一固态电极图案来增加半导体电容器的电容的方法，以有效增加所述第一电极图案的表面积的方式蚀刻所述第一电极图案上的地形特征， 所述电极图案上的电介质层基本上符合所述形貌特征，并且在所述电介质层上沉积第二固态电极图案，并且与所述第一固态电极图案充分绝缘，从而产生具有所述第一固态的电容 电极图案。

公开(公告)号：US06506660B2

公开(公告)日：2003-01-14

申请号：US10008092

申请日：2001-11-13

申请人： Steven J. Holmes ,  Charles Black ,  David J. Frank ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  William Hsioh-Lien Ma ,  Keith R. Milkove ,  Kathryn W. Guarini

发明人： Steven J. Holmes ,  Charles Black ,  David J. Frank ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  William Hsioh-Lien Ma ,  Keith R. Milkove ,  Kathryn W. Guarini

IPC分类号： H01L2120

CPC分类号： H01L28/92

摘要： Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

摘要翻译： 描述了通过在半导体介质上提供第一固态电极图案来增加半导体电容器的电容的方法，以有效增加所述第一电极图案的表面积的方式蚀刻所述第一电极图案上的地形特征， 所述电极图案上的电介质层基本上符合所述形貌特征，并且在所述电介质层上沉积第二固态电极图案，并且与所述第一固态电极图案充分绝缘，从而产生具有所述第一固态的电容 电极图案。

公开(公告)号：US06255178B1

公开(公告)日：2001-07-03

申请号：US09368767

申请日：1999-08-05

申请人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  G03F7/095 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/6659

摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

摘要翻译： 本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。 特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。 升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。 用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。 然后通过生长硅将源极区和漏极区连接到衬底。 因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

公开(公告)号：US6100013A

公开(公告)日：2000-08-08

申请号：US71207

申请日：1998-05-01

申请人： Jeffery S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffery S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L29/78 ,  G03F7/095 ,  G03F7/38 ,  H01L21/027 ,  H01L21/265 ,  H01L21/311 ,  H01L21/336 ,  G03F7/20

CPC分类号： H01L29/66492 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/6659 ,  G03F7/095 ,  H01L21/26586

摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

摘要翻译： 本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。 特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。 升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。 用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。 然后通过生长硅将源极区和漏极区连接到衬底。 因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

公开(公告)号：US06420766B1

公开(公告)日：2002-07-16

申请号：US09368843

申请日：1999-08-05

申请人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L2976

CPC分类号： H01L29/66492 ,  G03F7/095 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/6659

摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

摘要翻译： 本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。 特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。 升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。 用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。 然后通过生长硅将源极区和漏极区连接到衬底。 因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

公开(公告)号：US08039334B2

公开(公告)日：2011-10-18

申请号：US12902944

申请日：2010-10-12

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

IPC分类号： H01L21/8234

CPC分类号： H01L21/823412 ,  B01J23/74 ,  B01J37/0238 ,  B82Y10/00 ,  H01L21/7624 ,  H01L21/823437 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/763

摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.

摘要翻译： 在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。 所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管 晶体管位于至少一个平面半导体器件的栅极之上。

公开(公告)号：US08004024B2

公开(公告)日：2011-08-23

申请号：US12348404

申请日：2009-01-05

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L29/423 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/4908 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78621 ,  Y10S977/742 ,  Y10S977/847

摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.

摘要翻译： 晶体管。 晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

公开(公告)号：US07922796B2

公开(公告)日：2011-04-12

申请号：US12652908

申请日：2010-01-06

申请人： Steven J. Holmes ,  Mark C. Hakey ,  David V. Horak ,  James G. Ryan

发明人： Steven J. Holmes ,  Mark C. Hakey ,  David V. Horak ,  James G. Ryan

IPC分类号： B01D59/26

CPC分类号： B01D53/02 ,  B01D2253/102 ,  B01D2253/304 ,  B01J20/20 ,  B01J20/205 ,  B01J20/3242 ,  B82Y30/00 ,  Y10S55/05 ,  Y10S977/742 ,  Y10S977/745 ,  Y10S977/748 ,  Y10S977/75 ,  Y10S977/752

摘要： A carbon nanotube filter. The filter including a filter housing; and chemically active carbon nanotubes within the filter housing, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and media containing the chemically active carbon nanotubes.

摘要翻译： 碳纳米管过滤器。 过滤器包括过滤器壳体; 和化学活性碳纳米管，所述化学活性碳纳米管包括在碳纳米管上形成的化学活性层或在碳纳米管的侧壁上包含化学反应性基团; 和含有化学活性碳纳米管的介质。