公开(公告)号：US07517720B2

公开(公告)日：2009-04-14

申请号：US11984941

申请日：2007-11-26

申请人： Tetsuya Yamamoto ,  Atsutoshi Arakawa ,  Kenji Sato ,  Toshiaki Asahi

发明人： Tetsuya Yamamoto ,  Atsutoshi Arakawa ,  Kenji Sato ,  Toshiaki Asahi

IPC分类号： H01L21/00

CPC分类号： C30B29/48 ,  C30B23/002 ,  C30B25/02 ,  H01L21/02411 ,  H01L21/0248 ,  H01L21/02554 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/02568 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02623 ,  H01L21/02631 ,  H01L29/227 ,  H01L33/285

摘要： The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.

公开(公告)号：US07516075B2

公开(公告)日：2009-04-07

申请号：US10154289

申请日：2002-05-23

申请人： Tetsuya Yamamoto

发明人： Tetsuya Yamamoto

IPC分类号： G10L21/06

CPC分类号： G10L13/00

摘要： A hypersound document which insures reductions in cost and power requirement of electronic information terminals and a reproducer therefor. The hypersound document has plural pieces of voice data, a time table, and link destinations therein. In an embodiment shown in FIG. 1, “Sound1” for a piece of voice data, a start (t1) and an end (T1) for a time table, and “URL1” for a link destination are associated and stored.

公开(公告)号：US20080316696A1

公开(公告)日：2008-12-25

申请号：US11767801

申请日：2007-06-25

申请人： Taku NISHIYAMA ,  Kiyokazu Okada ,  Yoriyasu Ando ,  Tetsuya Yamamoto ,  Naohisa Okumura

发明人： Taku NISHIYAMA ,  Kiyokazu Okada ,  Yoriyasu Ando ,  Tetsuya Yamamoto ,  Naohisa Okumura

IPC分类号： H05K7/02

CPC分类号： H01L27/105 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/11517 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.

摘要翻译： 半导体存储器件设置有包括元件安装部分和连接焊盘的布线板。 多个半导体存储元件堆叠在布线板的元件安装部分上。 下侧的半导体存储元件的厚度大于上侧的半导体存储元件的厚度。 半导体存储元件通过金属线电连接到布线板的连接焊盘。

公开(公告)号：US20080217769A1

公开(公告)日：2008-09-11

申请号：US12022865

申请日：2008-01-30

申请人： Yasuyuki Yanase ,  Yoshio Okayama ,  Kiyoshi Shibata ,  Yasunori Inoue ,  Hideki Mizuhara ,  Ryosuke Usui ,  Tetsuya Yamamoto ,  Masurao Yoshii

发明人： Yasuyuki Yanase ,  Yoshio Okayama ,  Kiyoshi Shibata ,  Yasunori Inoue ,  Hideki Mizuhara ,  Ryosuke Usui ,  Tetsuya Yamamoto ,  Masurao Yoshii

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/94 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/274 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00014

摘要： An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area.The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

摘要翻译： 在半导体模块中的半导体衬底的安装表面（特别是其外周）上形成用于半导体器件的电极。 为了确保电极之间的大间隙，在电极上形成绝缘层。 还形成有穿过绝缘层并连接到电极的多个凸块，以及与凸块一体形成的重新布线图案。 重新布线图案包括凸起区域和与凸起区域相邻延伸的布线区域。 绝缘层形成为具有在凸起之间的间隔中的凹的上表面，并且重新布线图案的布线区域形成为适合该上表面。 重布线图案的布线区域相对于重新布线图案的凸起区域形成为朝向半导体基板压下。

公开(公告)号：US07393137B2

公开(公告)日：2008-07-01

申请号：US10567429

申请日：2004-09-30

申请人： Yasuhiro Hayashi ,  Isamu Kobayashi ,  Tetsuya Yamamoto

发明人： Yasuhiro Hayashi ,  Isamu Kobayashi ,  Tetsuya Yamamoto

IPC分类号： G01K1/00 ,  G01K7/00 ,  G08B6/00

CPC分类号： G01K13/002

摘要： A temperature measuring element (2a) for detecting a temperature, a display panel (9) for displaying the temperature measured by the temperature measuring element (2a), an operation switch (11) for predetermined operation, and a vibration generator (12) for notifying that an electronic clinical thermometer is in a predetermined state are arranged in the order named in the longitudinal direction of the electronic clinical thermometer. The display panel, the vibration generator, and a circuit board are held in one inside frame (13), and are fitted together with the inside frame (13) into a sheath case (1) and assembled.

摘要翻译： 用于检测温度的温度测量元件（2a），用于显示由温度测量元件（2a）测量的温度的显示面板（9），用于预定操作的操作开关（11）和振动发生器（12） ）用于通知电子体温计处于预定状态的顺序以按电子体温计的纵向方向命名。 显示面板，振动发生器和电路板保持在一个内框架（13）中，并与内框架（13）一起装配到护套壳体（1）中并组装。

公开(公告)号：US20080090390A1

公开(公告)日：2008-04-17

申请号：US11984944

申请日：2007-11-26

申请人： Tetsuya Yamamoto ,  Atsutoshi Arakawa ,  Kenji Sato ,  Toshiaki Asahi

发明人： Tetsuya Yamamoto ,  Atsutoshi Arakawa ,  Kenji Sato ,  Toshiaki Asahi

IPC分类号： H01L21/20

CPC分类号： C30B29/48 ,  C30B23/002 ,  C30B25/02 ,  H01L21/02411 ,  H01L21/0248 ,  H01L21/02554 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/02568 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02623 ,  H01L21/02631 ,  H01L29/227 ,  H01L33/285

摘要： The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.

摘要翻译： 本发明涉及一种具有高载流子浓度和低电阻率的n型ZnTe系化合物半导体单晶的制造方法，ZnTe系化合物半导体单晶以及使用ZnTe系化合物半导体作为基底制造的半导体装置 会员。 具体地，第一掺杂剂和第二掺杂剂共掺杂到ZnTe系化合物半导体单晶中，使得第二掺杂剂的原子数小于第一掺杂剂的原子数，第一掺杂剂用于控制 ZnTe系化合物半导体的导电类型为第一导电类型，第二掺杂剂用于将导电类型控制为不同于第一导电类型的第二导电类型。 通过本发明，可以实现与早期技术相比掺杂量小的期望载流子浓度，并且可以提高所得晶体的结晶度。

公开(公告)号：US20080089831A1

公开(公告)日：2008-04-17

申请号：US11984950

申请日：2007-11-26

申请人： Tetsuya Yamamoto ,  Atsutoshi Arakawa ,  Kenji Sato ,  Toshiaki Asahi

发明人： Tetsuya Yamamoto ,  Atsutoshi Arakawa ,  Kenji Sato ,  Toshiaki Asahi

IPC分类号： C01B19/00

CPC分类号： C30B29/48 ,  C30B23/002 ,  C30B25/02 ,  H01L21/02411 ,  H01L21/0248 ,  H01L21/02554 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/02568 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02623 ,  H01L21/02631 ,  H01L29/227 ,  H01L33/285

摘要： The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.

公开(公告)号：US07358159B2

公开(公告)日：2008-04-15

申请号：US10472446

申请日：2002-03-20

申请人： Tetsuya Yamamoto ,  Atsutoshi Arakawa ,  Kenji Sato ,  Toshiaki Asahi

发明人： Tetsuya Yamamoto ,  Atsutoshi Arakawa ,  Kenji Sato ,  Toshiaki Asahi

IPC分类号： H01L21/00

CPC分类号： C30B29/48 ,  C30B23/002 ,  C30B25/02 ,  H01L21/02411 ,  H01L21/0248 ,  H01L21/02554 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/02568 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02623 ,  H01L21/02631 ,  H01L29/227 ,  H01L33/285

摘要： The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.

摘要翻译： 本发明涉及一种具有高载流子浓度和低电阻率的n型ZnTe系化合物半导体单晶的制造方法，ZnTe系化合物半导体单晶以及使用ZnTe系化合物半导体作为基底制造的半导体装置 会员。 具体地，第一掺杂剂和第二掺杂剂共掺杂到ZnTe系化合物半导体单晶中，使得第二掺杂剂的原子数小于第一掺杂剂的原子数，第一掺杂剂用于控制 ZnTe系化合物半导体的导电类型为第一导电类型，第二掺杂剂用于将导电类型控制为不同于第一导电类型的第二导电类型。 通过本发明，可以实现与早期技术相比掺杂量小的期望载流子浓度，并且可以提高所得晶体的结晶度。

公开(公告)号：US07292761B2

公开(公告)日：2007-11-06

申请号：US10553842

申请日：2004-04-16

申请人： Kazuyuki Miyake ,  Syunichiro Yamaguchi ,  Tetsuya Yamamoto

发明人： Kazuyuki Miyake ,  Syunichiro Yamaguchi ,  Tetsuya Yamamoto

IPC分类号： G02B6/032 ,  G02B6/26

CPC分类号： G02B6/2552 ,  G02B6/02333 ,  G02B6/02347 ,  G02B6/262 ,  G02B6/32

摘要： A connection end portion of a PC fiber 10 is fused by heating to provide a sealing portion 15 which seals holes 12a of a cladding 12. Length L of the sealing portion 15 is determined by calculation based on the conditions such as an incident angle θ [°] of signal light 22 with respect to the PC fiber 10, an outer diameter D [μm] of the fiber, a diameter a [μm] of the core of the fiber and a refractive index n of the sealing portion 15.

摘要翻译： PC纤维10的连接端部通过加热熔合，以提供密封包层12的孔12a的密封部分15。 密封部分15的长度L通过基于诸如信号光22相对于PC纤维10的入射角θ[°]，纤维的外径D [mum]，直径a [mum]纤维的芯部和密封部分15的折射率n。

公开(公告)号：US07263388B2

公开(公告)日：2007-08-28

申请号：US09894883

申请日：2001-06-29

申请人： Tetsuya Yamamoto

发明人： Tetsuya Yamamoto

IPC分类号： H04M1/00 ,  H04B1/16 ,  H02J7/00

CPC分类号： H02J7/0027 ,  H02J7/02 ,  H02J7/025 ,  H04M1/04

摘要： A wall (103 in FIG. 1) is erected perpendicularly to a floor (101), and a charger body (105) in which a primary side coil (201) and a power feed portion (203) are included is mounted on the wall (103). An induction core (107) stretches in the shape of a hook from the charger body (105), and it penetrates through the primary side coil (201) inside the charger body (105). The induction core (107) can suspend a portable telephone (109) and another portable equipment (111) through charging arches (113).

摘要翻译： 一个壁（图1中的103）垂直于地板（101）竖立，并且其中包括一次侧线圈（201）和馈电部分（203）的充电器主体（105）安装在壁 （103）。 感应芯（107）从充电体（105）延伸成钩形，穿过充电器主体（105）内的初级侧线圈（201）。 感应芯（107）可以通过充电拱（113）悬挂便携式电话（109）和另一个便携式设备（111）。