公开(公告)号：US20070054462A1

公开(公告)日：2007-03-08

申请号：US11491907

申请日：2006-07-25

申请人： Tohru Ozaki ,  Yoshinori Kumura ,  Yoshiro Shimojo ,  Susumu Shuto

发明人： Tohru Ozaki ,  Yoshinori Kumura ,  Yoshiro Shimojo ,  Susumu Shuto

IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L21/00

CPC分类号： H01L27/11507 ,  H01L21/76834 ,  H01L21/76888 ,  H01L27/11502 ,  H01L28/57 ,  H01L28/65

摘要： A semiconductor device comprises an insulation film that is provided on a semiconductor substrate, a first contact plug that is provided in the insulation film and includes a metal, a first adhesive film that is provided on the insulation film, has a higher oxygen affinity than the metal, and includes an oxide, a second adhesive film that is provided on the first contact plug and has a film thickness that is smaller than a film thickness of the first adhesive film, a first capacitor electrode that is provided on the contact plug and the first adhesive film, has a part in direct contact with the first contact plug, a capacitor insulation film that is provided on the first capacitor electrode, and a second capacitor electrode that is provided on the capacitor insulation film.

摘要翻译： 半导体器件包括设置在半导体衬底上的绝缘膜，设置在绝缘膜中并且包括金属的第一接触插塞，设置在绝缘膜上的第一粘合膜具有比该绝缘膜更高的氧亲和力 金属，并且包括氧化物，第二粘合膜，其设置在第一接触插塞上并且具有小于第一粘合膜的膜厚度的膜厚度;设置在接触插塞上的第一电容器电极和 第一粘合膜具有与第一接触插塞直接接触的部分，设置在第一电容器电极上的电容器绝缘膜和设置在电容器绝缘膜上的第二电容器电极。

公开(公告)号：US07091537B2

公开(公告)日：2006-08-15

申请号：US10933382

申请日：2004-09-03

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L29/76

CPC分类号： H01L27/1159 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/11502 ,  H01L27/11585

摘要： A ferroelectric memory device includes a first trench formed in a semiconductor substrate and having a first depth, a second trench formed in the substrate and having a second depth, a first element isolation insulating film buried in the first trench, a first gate electrode formed in a lower region of the second trench, a first insulating film formed in an upper region of the second trench, first and second diffusion layers formed in the substrate on both side surface in the second trench, a first ferroelectric capacitor disposed on the first diffusion layer, a first contact disposed on the first ferroelectric capacitor, a first wiring layer disposed on the first contact, a second contact disposed on the second diffusion layer, and a second wiring layer disposed on the second contact and disposed in the same level as that of the first wiring layer.

摘要翻译： 铁电存储器件包括形成在半导体衬底中并具有第一深度的第一沟槽，形成在衬底中并具有第二深度的第二沟槽，埋在第一沟槽中的第一元件隔离绝缘膜，形成在第一沟槽中的第一栅电极 第二沟槽的下部区域，形成在第二沟槽的上部区域中的第一绝缘膜，在第二沟槽的两侧面上形成在基板中的第一和第二扩散层，设置在第一扩散层上的第一铁电电容器 设置在第一铁电电容器上的第一触点，设置在第一触点上的第一布线层，设置在第二扩散层上的第二触点和设置在第二触点上的第二布线层， 第一布线层。

公开(公告)号：US07042037B1

公开(公告)日：2006-05-09

申请号：US10986060

申请日：2004-11-12

申请人： Hiroshi Itokawa ,  Koji Yamakawa ,  Tohru Ozaki ,  Yoshinori Kumura ,  Takamichi Tsuchiya ,  Nicolas Nagel ,  Bum-Ki Moon ,  Andreas Hilliger

发明人： Hiroshi Itokawa ,  Koji Yamakawa ,  Tohru Ozaki ,  Yoshinori Kumura ,  Takamichi Tsuchiya ,  Nicolas Nagel ,  Bum-Ki Moon ,  Andreas Hilliger

IPC分类号： H01L31/062

CPC分类号： H01L28/55 ,  G11C11/22 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，设置在半导体衬底上方并包括底电极，顶电极和设置在底电极和顶电极之间的电介质膜的电容器，底电极包括含有 铱，设置在电介质膜和第一导电膜之间并由贵金属膜形成的第二导电膜，设置在电介质膜和第二导电膜之间并由具有钙钛矿结构的金属氧化物膜形成的第三导电膜， 以及设置在所述第一导电膜和所述第二导电膜之间并且包括金属膜和金属氧化物膜中的至少一种的防扩散膜，所述扩散防止膜防止包含在所述第一导电膜中的铱的扩散。

公开(公告)号：US20060030110A1

公开(公告)日：2006-02-09

申请号：US10959223

申请日：2004-10-07

申请人： Yoshinori Kumura ,  Iwao Kunishima ,  Tohru Ozaki

发明人： Yoshinori Kumura ,  Iwao Kunishima ,  Tohru Ozaki

IPC分类号： H01L21/336

CPC分类号： H01L29/945 ,  H01L27/11502 ,  H01L27/11507 ,  H01L29/66181

摘要： A semiconductor device including a ferroelectric random access memory, which has a structure suitable for miniaturization and easy to manufacture, and having less restrictions on materials to be used, comprises a field effect transistor formed on a surface area of a semiconductor wafer, a trench ferroelectric capacitor formed in the semiconductor wafer in one source/drain of the field effect transistor, wherein one electrode thereof is connected to the source/drain, and a wiring formed in the semiconductor wafer and connected to the other electrode of the trench ferroelectric capacitor.

摘要翻译： 包括具有适于小型化和易于制造的结构并且对材料的限制较少的铁电随机存取存储器的半导体器件包括形成在半导体晶片的表面区域上的场效应晶体管，沟槽铁电体 电容器形成在场效应晶体管的一个源极/漏极中的半导体晶片中，其中一个电极连接到源极/漏极，以及形成在半导体晶片中并连接到沟槽铁电电容器的另一个电极的布线。

公开(公告)号：US20060002170A1

公开(公告)日：2006-01-05

申请号：US10931193

申请日：2004-09-01

申请人： Yoshinori Kumura ,  Yoshiro Shimojo ,  Iwao Kunishima ,  Tohru Ozaki

发明人： Yoshinori Kumura ,  Yoshiro Shimojo ,  Iwao Kunishima ,  Tohru Ozaki

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/65

摘要： A semiconductor storage device wherein a plurality of ferroelectric capacitors are sufficiently covered with a hydrogen barrier film formed thereon comprises a field effect transistor formed on one surface side of a semiconductor substrate, a plurality of ferroelectric capacitors formed close to each other above the field effect transistor, an insulting film configured to cover the plurality of ferroelectric capacitors and planarised a space between adjacent ferroelectric capacitors in a self-aligned manner during formation thereof, and a hydrogen barrier film formed on the insulating film.

公开(公告)号：US06635933B2

公开(公告)日：2003-10-21

申请号：US09953306

申请日：2001-09-17

申请人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

发明人： Yutaka Ishibashi ,  Yusuke Kohyama ,  Tohru Ozaki

IPC分类号： H01L2976

CPC分类号： H01L27/10885 ,  H01L27/10852 ,  H01L27/10873 ,  H01L28/91

摘要： Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.

公开(公告)号：US06521929B2

公开(公告)日：2003-02-18

申请号：US09816245

申请日：2001-03-26

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27108

CPC分类号： H01L27/11502 ,  H01L21/76838 ,  H01L28/55

摘要： A semiconductor device having ferroelectric memory cells has memory cell transistors each including first and second source/drain regions. Plug electrodes are formed in contact with the first and second source/drain regions, respectively. A ferroelectric capacitor is formed on the plug electrode connected to the first source/drain region. The ferroelectric capacitor includes a first lower electrode formed on the plug electrode, a ferroelectric film formed on the first lower electrode, and an upper electrode formed on the ferroelectric film. A second lower electrode is formed on the plug electrode connected to the second source/drain region. Wiring is formed to connect the upper electrode to the corresponding second lower electrode.

公开(公告)号：US06180973B2

公开(公告)日：2001-01-30

申请号：US09069853

申请日：1998-04-30

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27108

CPC分类号： H01L27/10867 ,  H01L27/10832 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10873 ,  H01L27/10891

摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation film formed on the substrate, element formation regions each defined in an island form in the surface of the substrate by the element isolation film, trenches formed in the element formation regions, respectively, capacitors each formed in a corresponding one of the trenches, each having a plate electrode formed of the substrate, a capacitor insulating film formed on the inner wall of the trench and a storage electrode filled in the trench with the capacitor insulating film disposed therebetween, transistors each formed in the element formation regions, and having a gate electrode which is formed to extend over the substrate and pass over the trench and the element formation region, a first impurity diffusion layer formed on one side of the gate electrode, a second impurity diffusion layer formed on the other side of the gate electrode, and channel regions formed on the element formation region on both sides of the trench below the gate electrode and respectively connected to the first and second impurity diffusion layers, connection electrodes for respectively connecting the storage electrodes to the first impurity diffusion layers, and signal transmission lines respectively connected to the second impurity diffusion layers.

摘要翻译： 半导体存储器件包括半导体衬底，形成在衬底上的元件隔离膜，通过元件隔离膜在衬底的表面中以岛状形成的元件形成区域，分别形成在元件形成区域中的沟槽，电容器 每个形成在对应的一个沟槽中，每个沟槽具有由衬底形成的平板电极，形成在沟槽的内壁上的电容器绝缘膜和填充在沟槽中的存储电极，其间设置有电容器绝缘膜，晶体管各自 形成在所述元件形成区域中，并且具有形成为在所述基板上延伸并越过所述沟槽和所述元件形成区域的栅电极，形成在所述栅电极的一侧上的第一杂质扩散层，第二杂质扩散层 形成在栅电极的另一侧上，以及形成在元件形成区上的沟道区 并且分别连接到第一和第二杂质扩散层，用于将存储电极分别连接到第一杂质扩散层的连接电极和分别连接到第二杂质扩散层的信号传输线。

公开(公告)号：US6162720A

公开(公告)日：2000-12-19

申请号：US217947

申请日：1998-12-22

申请人： Tohru Ozaki

发明人： Tohru Ozaki

IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L27/10852 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10861

摘要： A method of manufacturing a semiconductor device. First, a plurality of wires are arranged in parallel to one another, on a semiconductor substrate. Then, insulating films of a first group are formed on tops of the wires, respectively. Next, second insulating films of a second group are formed on sides of the wires, respectively. Further, among the wires there are formed insulating films of a third group which have upper surfaces located at a level not higher than upper surfaces of the insulating films of the second group. Thereafter, contact holes are formed by subjecting the insulating films of the third group to selectively etching. Finally, the contact holes are filled with electrically conductive material.

摘要翻译： 一种制造半导体器件的方法。 首先，在半导体基板上并列配置多条电线。 然后，分别在导线的顶部形成第一组的绝缘膜。 接下来，第二组的第二绝缘膜分别形成在导线的侧面上。 此外，在导线之间形成具有位于不高于第二组的绝缘膜的上表面的上表面的第三组的绝缘膜。 此后，通过对第三组的绝缘膜进行选择性蚀刻来形成接触孔。 最后，接触孔填充有导电材料。

公开(公告)号：US6078073A

公开(公告)日：2000-06-20

申请号：US878208

申请日：1997-06-18

申请人： Mariko Habu ,  Kazumasa Sunouchi ,  Masami Aoki ,  Tohru Ozaki

发明人： Mariko Habu ,  Kazumasa Sunouchi ,  Masami Aoki ,  Tohru Ozaki

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10844 ,  H01L21/76897 ,  H01L27/10873

摘要： A gate electrode having a first insulating film laminated in the upper portion thereof is formed on a gate insulating film formed on a semiconductor substrate. A side wall is formed on the side wall of the gate electrode, and an insulating film is formed to cover the gate electrode and the side wall. Ion implantation is performed through the insulating film so that a diffusion layer is formed on the semiconductor substrate. An interlayer dielectric film is formed, and then the interlayer dielectric film and the insulating film are selectively etched so that an opening portion for exposing the gate insulating film is formed in a self-align manner with the gate electrode. Then, the gate insulating film in the bottom portion of the opening portion is removed so that the surface of the semiconductor substrate is exposed. Then, a wiring layer connected to the exposed surface of the semiconductor substrate is formed.

摘要翻译： 在形成在半导体衬底上的栅绝缘膜上形成具有层叠在其上部的第一绝缘膜的栅电极。 在栅电极的侧壁上形成侧壁，并且形成绝缘膜以覆盖栅电极和侧壁。 通过绝缘膜进行离子注入，从而在半导体衬底上形成扩散层。 形成层间电介质膜，然后选择性地蚀刻层间电介质膜和绝缘膜，从而以与栅电极自对准的方式形成露出栅极绝缘膜的开口部。 然后，去除开口部的底部的栅极绝缘膜，使得露出半导体基板的表面。 然后，形成与半导体基板的露出面连接的布线层。