公开(公告)号：US20240038693A1

公开(公告)日：2024-02-01

申请号：US18482002

申请日：2023-10-05

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L23/66 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/66 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0652 ,  H01L2223/6605 ,  H01L2224/08145 ,  H01L2224/80894 ,  H01L2924/14215 ,  H01L2924/2027

Abstract: A semiconductor structure including chips is provided. The chips are arranged in a stack. Each of the chips includes a radio frequency (RF) device. Two adjacent chips are bonded to each other. The RF devices in the chips are connected in parallel. Each of the RF devices includes a gate, a source region, and a drain region. The gates in the RF devices connected in parallel have the same shape and the same size. The source regions in the RF devices connected in parallel have the same shape and the same size. The drain regions in the RF devices connected in parallel have the same shape and the same size.

公开(公告)号：US20230299174A1

公开(公告)日：2023-09-21

申请号：US17724511

申请日：2022-04-20

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L29/66 ,  H01L29/737 ,  H01L23/528 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L29/66242 ,  H01L29/737 ,  H01L23/5283 ,  H01L29/0649 ,  H01L21/76898

Abstract: A semiconductor structure includes following components. A first substrate has a first surface and a second surface opposite to each other. An HBT device is located on the first substrate and includes a collector, a base, and an emitter. A first interconnect structure is electrically connected to the base, located on the first surface, and extends to the second surface. A second interconnect structure is electrically connected to the emitter, located on the first surface, and extends to the second surface. A third interconnect structure is located on the second surface and electrically connected to the collector. An MOS transistor device is located on a second substrate and includes a gate, a first source and drain region, and a second source and drain region. Interconnect structures on the second substrate electrically connect the base to the first source and drain region and electrically connect the emitter to the gate.

公开(公告)号：US11462618B2

公开(公告)日：2022-10-04

申请号：US17191720

申请日：2021-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hai Biao Yao ,  Su Xing

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L21/266 ,  H01L21/265 ,  H01L29/167

Abstract: An SOI semiconductor device includes a substrate, a buried oxide layer disposed on the substrate, a top semiconductor layer disposed on the buried oxide layer, a source doping region and a drain doping region in the top semiconductor layer, a channel region between the source doping region and the drain doping region in the top semiconductor layer, a gate electrode on the channel region, and an embedded doping region disposed in the top semiconductor layer and directly under the channel region. The embedded doping region acts as a hole sink to alleviate or avoid floating body effects.

公开(公告)号：US10546631B1

公开(公告)日：2020-01-28

申请号：US16208523

申请日：2018-12-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/419

Abstract: A static random access memory (SRAM) cell structure includes a first inverter. The first inverter includes a first transistor and a second transistor. The first transistor includes a first source electrode and a first drain electrode. The first source electrode is connected to a first voltage source. The first source electrode includes a first doped region and a second doped region disposed in the first doped region, and a conductivity type of the second doped region is complementary to a conductivity type of the first doped region. The first drain electrode is connected to a first storage node. The second transistor includes a second source electrode and a second drain electrode. The second source electrode is connected to a second voltage source. The second drain electrode is connected to the first storage node.

公开(公告)号：US20190109200A1

公开(公告)日：2019-04-11

申请号：US15802419

申请日：2017-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L29/49 ,  H01L23/66 ,  H01L29/06

CPC classification number: H01L29/4933 ,  H01L23/66 ,  H01L29/0607 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/78651

Abstract: A radiofrequency switch device includes an insulation layer, a semiconductor layer, a gate structure, a first doped region, a second doped region, an epitaxial layer, a first silicide layer, and a second silicide layer. The semiconductor layer is disposed on the insulation layer. The gate structure is disposed on the semiconductor layer. The first doped region and the second doped region are disposed in the semiconductor layer at two opposite sides of the gate structure respectively. The epitaxial layer is disposed on the first doped region. The first silicide layer is disposed on the epitaxial layer. The second silicide layer is disposed in the second doped region.

公开(公告)号：US20180190714A1

公开(公告)日：2018-07-05

申请号：US15849563

申请日：2017-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/8234 ,  H01L29/786

CPC classification number: H01L27/2436 ,  H01L21/82345 ,  H01L29/7869 ,  H01L45/065 ,  H01L45/122 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer and a drain layer adjacent two sides of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.

公开(公告)号：US09997627B2

公开(公告)日：2018-06-12

申请号：US15709450

申请日：2017-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/78 ,  H01L29/24 ,  H01L21/467 ,  H01L21/441 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/441 ,  H01L21/467 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/7869

Abstract: A semiconductor device includes: a channel layer surrounded by a source layer; a first dielectric layer around the source layer; a gate layer around the channel layer and on the source layer; a first oxide semiconductor layer between the gate layer and the channel layer; a second oxide semiconductor layer between the gate layer and the drain layer; a second gate dielectric layer between the second oxide semiconductor layer and the drain layer; a drain layer on the gate layer and around the channel layer; and a second dielectric layer around the drain layer.

公开(公告)号：US20180145081A1

公开(公告)日：2018-05-24

申请号：US15361070

申请日：2016-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/4125 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1116

Abstract: The present invention provides a SRAM unit cell which includes a semiconductor substrate, six transistors, a first well, two first doped regions and two second doped regions. The transistors are disposed on the semiconductor substrate, and include a first gate line and a second gate line. The first well is disposed in the semiconductor substrate, and the first well has a first conductive type, wherein the first gate line and the second gate line extend onto the first well. The first doped regions are disposed in the first well at two sides of the first gate line, and the second doped regions are disposed in the first well at two sides of the second gate line.

公开(公告)号：US09871049B1

公开(公告)日：2018-01-16

申请号：US15593345

申请日：2017-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L29/06 ,  H01L47/00 ,  H01L27/11 ,  H01L23/48 ,  H01L45/00 ,  H01L27/24 ,  H01L23/525 ,  H01L23/532 ,  G11C14/00 ,  G11C11/419

CPC classification number: H01L27/1116 ,  G11C11/419 ,  G11C14/009 ,  H01L23/481 ,  H01L23/525 ,  H01L23/532 ,  H01L27/1104 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

Abstract: A static random access memory device includes two body contacts and two resistive-switching devices. The body contacts are disposed in a wafer and are exposed from a back side of the wafer, wherein the body contacts electrically connect a static random access memory cell through a metal interconnect in the wafer. The resistive-switching devices connect the two body contacts respectively from the back side of the wafer. A method of forming a static random access memory device is also provided in the following. A wafer having two body contacts exposed from a back side of the wafer and a metal interconnect electrically connecting a static random access memory cell to the body contacts is provided. Two resistive-switching devices are formed to connect the two body contacts respectively from the back side of the wafer.

公开(公告)号：US20180006129A1

公开(公告)日：2018-01-04

申请号：US15628592

申请日：2017-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Hsueh-Wen Wang ,  Chien-Yu Ko ,  Yu-Cheng Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yu-Ming Lin

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/516 ,  H01L21/28291 ,  H01L27/11585 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7869

Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.