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51.发明授权Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode 有权用三字节转义操作码来排除指令特定操作码的地址格式字段的指令长度公开(公告)号：US08161269B2
公开(公告)日：2012-04-17
申请号：US13070908
申请日：2011-03-24
申请人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
发明人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30185
摘要： A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
摘要翻译： 公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。 该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关 操作码地图。 对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。
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公开(公告)号：US07010665B1
公开(公告)日：2006-03-07
申请号：US10185513
申请日：2002-06-27
IPC分类号： G06F12/02
CPC分类号： G06F9/322 , G06F9/30003 , G06F9/30054 , G06F9/3016 , G06F9/30167 , G06F9/3017 , G06F9/30178 , G06F9/324 , G06F9/342 , G06F9/3557 , G06F9/383
摘要： A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed relative address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.
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53.发明授权公开(公告)号：US06775786B2
公开(公告)日：2004-08-10
申请号：US09951908
申请日：2001-09-12
申请人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
发明人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
IPC分类号： G06F126
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/329 , Y02D10/128 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.
摘要翻译： 一种用于多线程处理器中功率模式转换的方法和装置。 发布第一指示，包括与处理器中的第一逻辑处理器相关联的第一标识符，第一逻辑处理器已经进入功率模式。 发出第二指示，包括与处理器中的第二逻辑处理器相关联的第二标识符，第二逻辑处理器已经进入电源模式。 指示可以是例如停止授权确认特殊总线周期，指示逻辑处理器已经进入停止许可模式。 当第一和第二指示都已被发出时，处理器可以转换到睡眠模式。
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公开(公告)号：US10203954B2
公开(公告)日：2019-02-12
申请号：US13977732
申请日：2011-11-25
摘要： Instructions and logic provide conversions between a mask register and a general purpose register or memory. Some embodiments, responsive to an instruction specifying: a destination operand, a mask length corresponding to a number of mask data fields, and a source operand; values are read from data fields in the source operand, corresponding to the specified mask length, and stored to corresponding data fields in the destination operand specified by the instruction, wherein one of the source or the destination operands is a mask register. Values indicative of masked vector elements may be stored to any data fields in the destination operand other than the number of data fields corresponding to the specified mask length. For some embodiments, the other one of the source or the destination operands may be a general purpose register or a memory location.
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公开(公告)号：US10037205B2
公开(公告)日：2018-07-31
申请号：US13977734
申请日：2011-12-23
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/3887
摘要： Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a first selector portion and a second selector portion. Corresponding unmasked vector elements are stored to fields of the destination register, wherein each vector element, responsive to the respective first selector portion having a first value, is copied to an intermediate vector from a corresponding data field of the first register, and responsive to the respective first selector portion having a second value, is copied to the intermediate vector from a corresponding data field of the third operand. Then unmasked data fields of the destination are replaced by data fields in the intermediate vector indexed by the corresponding second selector portions.
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公开(公告)号：US09575757B2
公开(公告)日：2017-02-21
申请号：US13991858
申请日：2011-12-30
申请人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
发明人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
CPC分类号： G06F9/30018 , G06F9/30036 , H03M7/46
摘要： A processor core including a hardware decode unit to decode vector instructions for decompressing a run length encoded (RLE) set of source data elements and an execution unit to execute the decoded instructions. The execution unit generates a first mask by comparing set of source data elements with a set of zeros and then counts the trailing zeros in the mask. A second mask is made based on the count of trailing zeros. The execution unit then copies the set of source data elements to a buffer using the second mask and then reads the number of RLE zeros from the set of source data elements. The buffer is shifted and copied to a result and the set of source data elements is shifted to the right. If more valid data elements are in the set of source data elements this is repeated until all valid data is processed.
摘要翻译： 一种处理器核心，包括硬件解码单元，用于解码用于解压缩源数据元素的游程长度编码（RLE）集合的向量指令和执行单元以执行解码的指令。 执行单元通过将源数据元素的集合与一组零进行比较来生成第一掩码，然后计数掩码中的尾随零。 第二个掩码基于尾随零的计数。 执行单元然后使用第二掩码将源数据元素集合复制到缓冲器，然后从源数据元素集合读取RLE零的数目。 将缓冲区移位并复制到结果，并将源数据元素集合向右移动。 如果源数据元素集合中有更多有效的数据元素，则重复此操作，直到处理所有有效数据。
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57.发明授权Floating point round-off amount determination processors, methods, systems, and instructions 有权浮点数四舍五入确定处理器，方法，系统和说明公开(公告)号：US09513871B2
公开(公告)日：2016-12-06
申请号：US13977257
申请日：2011-12-30
CPC分类号： G06F9/3001 , G06F7/483 , G06F7/49947 , G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013
摘要： A method of an aspect includes receiving a floating point round-off amount determination instruction. The instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point, and indicates a destination storage location. A result including one or more result floating point data elements is stored in the destination storage location in response to the floating point round-off amount determination instruction. Each of the one or more result floating point data elements includes a difference between a corresponding floating point data element of the source in a corresponding position, and a rounded version of the corresponding floating point data element of the source that has been rounded to the indicated number of the fraction bits. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一种方面的方法包括接收浮点舍入量确定指令。 该指令指示一个或多个浮点数据元素的源，指示小数点之后的小数位数，并指示目的地存储位置。 包括一个或多个结果浮点数据元素的结果响应于浮点舍入量确定指令被存储在目的地存储位置中。 一个或多个结果浮点数据元素中的每一个包括相应位置的源的相应浮点数据元素与已被舍入到指示的源的相应浮点数据元素的舍入版本之间的差 小数位数。 公开了其它方法，装置，系统和指令。
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公开(公告)号：US09489196B2
公开(公告)日：2016-11-08
申请号：US13997998
申请日：2011-12-23
申请人： Mikhail Plotnikov , Andrey Naraikan , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Bret L. Toll , Jesus Corbal
发明人： Mikhail Plotnikov , Andrey Naraikan , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Bret L. Toll , Jesus Corbal
CPC分类号： G06F9/3013 , G06F7/764 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30036
摘要： A method is described that includes reading a first read mask from a first register. The method also includes reading a first vector operand from a second register or memory location. The method also includes applying the read mask against the first vector operand to produce a set of elements for operation. The method also includes performing an operation of the set elements. The method also includes creating an output vector by producing multiple instances of the operation's result. The method also includes reading a first write mask from a third register, the first write mask being different than the first read mask. The method also includes applying the write mask against the output vector to create a resultant vector. The method also includes writing the resultant vector to a destination register.
摘要翻译： 描述了一种包括从第一寄存器读取第一读取掩码的方法。 该方法还包括从第二寄存器或存储器位置读取第一向量操作数。 该方法还包括对第一向量操作数应用读取掩码以产生用于操作的一组元素。 该方法还包括执行设定元件的操作。 该方法还包括通过产生操作结果的多个实例来创建输出向量。 该方法还包括从第三寄存器读取第一写掩码，第一写掩码不同于第一读掩码。 该方法还包括针对输出向量应用写掩码以产生合成矢量。 该方法还包括将结果矢量写入目的地寄存器。
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59.发明授权公开(公告)号：US09354877B2
公开(公告)日：2016-05-31
申请号：US13992709
申请日：2011-12-23
CPC分类号： G06F9/30018 , G06F9/30025 , G06F9/30098 , G06F9/30181
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor mask bit compression in response to a single mask bit compression instruction that includes a source writemask register operand, a destination writemask register operand, and an opcode are described.
摘要翻译： 描述了在计算机处理器中执行屏蔽位压缩的系统，装置和方法的实施例，其响应于包括源写入寄存器操作数，目的地写入寄存器操作数和操作码的单个掩码位压缩指令。
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60.发明授权Packed data operation mask comparison processors, methods, systems, and instructions 有权打包数据操作掩码比较处理器，方法，系统和指令公开(公告)号：US09244687B2
公开(公告)日：2016-01-26
申请号：US13977153
申请日：2011-12-29
申请人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
发明人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
CPC分类号： G06F9/30189 , G06F9/30018 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30094 , G06F9/30101 , G06F9/30145
摘要： Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit of second mask in corresponding position. Modify first flag to first value if bitwise AND of each packed data operation mask bit of first mask with each corresponding packed data operation mask bit of second mask is zero. Otherwise modify first flag to second value. Modify second flag to third value if bitwise AND of each packed data operation mask bit of first mask with bitwise NOT of each corresponding packed data operation mask bit of second mask is zero. Otherwise modify second flag to fourth value.
摘要翻译： 接收指示具有第一打包数据操作屏蔽位的第一打包数据操作掩码的打包数据操作掩码比较指令和具有第二打包数据操作掩码位的第二打包数据操作掩码。 第一掩码的每个打包数据操作屏蔽位对应于相应位置的第二掩码的打包数据操作屏蔽位。 将第一个掩码的每个打包数据操作屏蔽位的按位AND和第二个掩码的每个对应的打包数据操作掩码位的第一个值修改为第一个值为零。 否则将第一个标志修改为第二个值。 如果第二掩码的每个对应的打包数据操作屏蔽位的按位NOT的第一掩码的每个打包数据操作屏蔽位的按位AND为零，则将第二标志修改为第三值。 否则将第二个标志修改为第四个值。
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