公开(公告)号：US20080250257A1

公开(公告)日：2008-10-09

申请号：US12038974

申请日：2008-02-28

申请人： Jeffrey S. Brown

发明人： Jeffrey S. Brown

IPC分类号： G06F1/26

CPC分类号： G06F1/3243 ,  G06F1/3225 ,  G06F1/3275 ,  G11C7/1006 ,  G11C7/22 ,  G11C16/10 ,  G11C16/26 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152

摘要： A method for conserving power in a device. The method generally includes the steps of (A) generating a polarity signal by analyzing a current one of a plurality of data items having a plurality of data bits, the polarity signal having an inversion bit indicating that the current data item is to be stored in one of (i) an inverted condition and (ii) a non-inverted condition relative to a normal condition such that a majority of the data bits have a first logic state, wherein reading one of the data bits having the first logic state consumes less power than reading one of the data bits having a second logic state, (B) selectively either (i) inverting the current data item or (ii) not inverting current the data item based on the inversion bit and (C) storing the current data item in a plurality of single-ended bit cells in the device.

摘要翻译： 一种节省设备功率的方法。 该方法通常包括以下步骤：（A）通过分析具有多个数据位的多个数据项中的当前一个数据项来产生极性信号，所述极性信号具有指示当前数据项将要存储的反转位 （i）反转条件和（ii）相对于正常条件的非反相条件之一，使得大多数数据位具有第一逻辑状态，其中读取具有第一逻辑状态的数据位中的一个消耗较少 （B）选择性地（i）反转当前数据项或（ii）基于反转位不反转当前数据项，（C）存储当前数据 项目在设备中的多个单端比特单元中。

公开(公告)号：US20080244474A1

公开(公告)日：2008-10-02

申请号：US11732092

申请日：2007-04-02

申请人： Mark F. Turner ,  Jonathan W. Byrn ,  Jeffrey S. Brown

发明人： Mark F. Turner ,  Jonathan W. Byrn ,  Jeffrey S. Brown

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method of managing a cell library regarding power optimization is disclosed. The method generally includes the steps of (A) reading a plurality of first modules within a first region of a circuit design stored in a design file, (B) calculating a first merit value indicating a relative sensitivity of the first region to a power consumption, the first merit value having a range from a static power dominated value to a dynamic power dominated value and (C) creating a constraint file configured to limit a design tool to a first subset of a plurality of replacement modules based on the first merit value such that the design tool automatically optimizes the power consumption of the first region by replacing at least one of the first modules with at least one of the replacement modules within the first subset, the replacement modules residing in a library file.

摘要翻译： 公开了一种管理关于功率优化的单元库的方法。 该方法通常包括以下步骤：（A）读取存储在设计文件中的电路设计的第一区域内的多个第一模块，（B）计算指示第一区域相对于功耗的相对灵敏度的第一优值值 所述第一优点值具有从静态功率主导值到动态功率主导值的范围，以及（C）创建约束文件，其被配置为基于所述第一优点值将设计工具限制到多个替换模块的第一子集 使得设计工具通过用第一子集内的至少一个替换模块替​​换至少一个第一模块来自动优化第一区域的功耗，所述替换模块驻留在库文件中。

公开(公告)号：US07131103B2

公开(公告)日：2006-10-31

申请号：US10793055

申请日：2004-03-04

申请人： Jeffrey S. Brown

发明人： Jeffrey S. Brown

IPC分类号： G06F17/50

CPC分类号： G03F1/00 ,  H01L27/0207

摘要： A method for integrating a first integrated circuit design having first layers and a second integrated circuit design having second layers into a common reticle set. The second integrated circuit design has a given number of second layers and the first integrated circuit design has less than the given number of layers. At least one of the first layers is duplicated to produce at least one duplicated first layer until the first integrated circuit design has the given number of layers. The first layers and the at least one duplicated first layer are mapped to a modified first integrated circuit design having the given number of first layers. A reticle set is fabricated to include the given number of first layers and second layers, using the modified first integrated circuit design and the second integrated circuit design.

摘要翻译： 一种用于将具有第一层的第一集成电路设计和具有第二层的第二集成电路设计集成到公共掩模版集合中的方法。 第二集成电路设计具有给定数量的第二层，并且第一集成电路设计具有小于给定数量的层。 第一层中的至少一个被复制以产生至少一个复制的第一层，直到第一集成电路设计具有给定数量的层。 第一层和至少一个复制的第一层被映射到具有给定数量的第一层的修改的第一集成电路设计。 使用修改的第一集成电路设计和第二集成电路设计，制作掩模版组以包括给定数量的第一层和第二层。

公开(公告)号：US06908291B2

公开(公告)日：2005-06-21

申请号：US10198927

申请日：2002-07-19

申请人： Manfred P. Klein ,  Jeffrey S. Brown ,  Scott A. McAloon

发明人： Manfred P. Klein ,  Jeffrey S. Brown ,  Scott A. McAloon

IPC分类号： F04D13/02 ,  F04D29/02 ,  F04B17/00 ,  F03D11/02

CPC分类号： F04D29/026 ,  F04D13/026 ,  F04D13/027 ,  F05D2260/95 ,  F05D2300/10 ,  F05D2300/43 ,  F05D2300/615 ,  H02K5/128 ,  H02K7/14 ,  H02K2005/1287 ,  Y10T29/49229 ,  Y10T29/49236 ,  Y10T29/49243

摘要： An impeller for a magnetic-drive centrifugal pump includes a core for supporting a magnetic assembly of magnets. An inner barrier covers at least part of the magnets. The inner barrier hermetically isolates the magnetic assembly within the impeller. For example, in one embodiment the inner barrier may be sealed or hermetically connected to the core at one or more seams. An outer barrier overlies the inner barrier.

摘要翻译： 用于磁驱动离心泵的叶轮包括用于支撑磁体的磁性组件的芯。 内部阻挡层覆盖至少部分磁体。 内部障碍物将叶片内的磁性组件隔离。 例如，在一个实施例中，内屏障可以在一个或多个接缝处被密封或密封地连接到芯。 外屏障覆盖内屏障。

公开(公告)号：US06700163B2

公开(公告)日：2004-03-02

申请号：US09683278

申请日：2001-12-07

申请人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

发明人： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

IPC分类号： H01L2976

CPC分类号： H01L21/823871 ,  H01L21/823842

摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.

摘要翻译： 本文公开了选择性硅化半导体结构及其制造方法。 半导体结构在N +扩散或N +有源区域之间的多晶硅线路上存在自杀，并且在多晶硅线路的N + / P +结处的P +扩散或有源区域存在自杀，并且在N +有源区域和P +活性区域上不存在硅化物 区。 这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。 在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

公开(公告)号：US06420766B1

公开(公告)日：2002-07-16

申请号：US09368843

申请日：1999-08-05

申请人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L2976

CPC分类号： H01L29/66492 ,  G03F7/095 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/6659

摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

摘要翻译： 本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。 特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。 升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。 用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。 然后通过生长硅将源极区和漏极区连接到衬底。 因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

公开(公告)号：US08125815B2

公开(公告)日：2012-02-28

申请号：US12337880

申请日：2008-12-18

申请人： Jeffrey S. Brown ,  Mark F. Turner

发明人： Jeffrey S. Brown ,  Mark F. Turner

IPC分类号： G11C17/00

CPC分类号： G11C8/10 ,  G11C17/12

摘要： An apparatus and method for providing a read-only memory (ROM) bit cell having one each of a PMOS transistor and an NMOS transistor, which has reduced static and dynamic electric power losses, are described. In particular, the bit cell does not require a pre-charge transistor. The sense amplifier for determining the voltages on ROM bit lines may be a digital inverter, address decoding may be simplified since there are no timing requirements with respect to transistor pre-charge, and chips containing a plurality of ROM bit cell may be readily programmed. In one embodiment of the invention, each bit cell includes one PMOS transistor having its source in electrical connection with a voltage source, its drain connected or unconnected to a bit line, and its gate connected to an inverted version of the word line signal; and one NMOS transistor having its source connected to a lower voltage source, its drain connected or disconnected to the bit line, and its gate connected to the word line. The bit cell is programmed during the ROM generation by connecting the drain of either the PMOS (logic level 1) or the NMOS (logic level 0) to the bit line.

摘要翻译： 描述了一种用于提供具有降低的静态和动态功率损耗的PMOS晶体管和NMOS晶体管中的每一个的只读存储器（ROM）位单元的装置和方法。 特别地，位单元不需要预充电晶体管。 用于确定ROM位线上的电压的读出放大器可以是数字反相器，由于没有关于晶体管预充电的定时要求，所以可以简化地址解码，并且可容易地编程包含多个ROM位单元的芯片。 在本发明的一个实施例中，每个位单元包括一个PMOS晶体管，其源极与电压源电连接，其漏极连接或未连接到位线，并且其栅极连接到字线信号的反相版本; 和一个NMOS晶体管，其源极连接到较低电压源，其漏极与位线连接或断开，其栅极连接到字线。 在ROM生成期间通过将PMOS（逻辑电平1）或NMOS（逻辑电平0）的漏极连接到位线来对位单元进行编程。

公开(公告)号：US20120023473A1

公开(公告)日：2012-01-26

申请号：US12840535

申请日：2010-07-21

申请人： Jeffrey S. Brown ,  Jonathan W. Byrn ,  Mark F. Turner

发明人： Jeffrey S. Brown ,  Jonathan W. Byrn ,  Mark F. Turner

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/78

摘要： A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint.

摘要翻译： 记录具有一个或多个可由计算机读取的单元的单元库的存储介质，并可由计算机用于设计集成电路。 一个或多个单元可以具有物理尺寸参数和通道宽度参数。 物理尺寸参数可以是一个或多个单元格的占位面积。 通道宽度参数可能具有最小驱动程序大小和最大驱动程序大小。 通道宽度参数可以定义范围，在该范围内，工具在集成电路的设计流程期间基于一个或多个功率准则改变最大驱动器尺寸和最小驱动器尺寸之间的通道宽度，而不改变占用面积。

公开(公告)号：US07818695B2

公开(公告)日：2010-10-19

申请号：US11962165

申请日：2007-12-21

申请人： Jonathan W. Byrn ,  Mark F. Turner ,  Jeffrey S. Brown

发明人： Jonathan W. Byrn ,  Mark F. Turner ,  Jeffrey S. Brown

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A method to redistribute current demand is presented. The method includes a first step of determining timing arc data for one or more timing arcs of a circuit design. The method includes a second step of checking the timing arc data for delay shift target cells. The method includes a further step of swapping a delay shift target cell with a delay shift cell.

摘要翻译： 介绍了一种重新分配当前需求的方法。 该方法包括确定电路设计的一个或多个定时弧的定时弧数据的第一步骤。 该方法包括检查用于延迟移位目标小区的定时弧数据的第二步骤。 该方法还包括用延迟移位单元交换延迟移位目标小区的另一步骤。

公开(公告)号：US20090288053A1

公开(公告)日：2009-11-19

申请号：US12119893

申请日：2008-05-13

申请人： Jeffrey S. Brown ,  Alan L. Ilolesovsky ,  Mark F. Turner

发明人： Jeffrey S. Brown ,  Alan L. Ilolesovsky ,  Mark F. Turner

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/84

摘要： Associated methods and a computer program product are disclosed for modifying a design of an integrated circuit. Properties are assigned to cells in an integrated circuit design. The properties include a location constraint property and a timing constraint property. When a cell is moved and one or more properties are not in compliance, other cells are moved to restore the non-compliant properties to compliance.

摘要翻译： 公开了相关方法和计算机程序产品，用于修改集成电路的设计。 集成电路设计中的属性分配给单元。 属性包括位置约束属性和时序约束属性。 当移动单元格并且一个或多个属性不符合时，将移动其他单元以将不合规属性恢复为合规性。