公开(公告)号：US07725755B1

公开(公告)日：2010-05-25

申请号：US11668353

申请日：2007-01-29

申请人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

发明人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

IPC分类号： G06F1/00 ,  G06F1/14

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/108 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091

摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.

摘要翻译： 用于延迟多数据速率接口的时钟信号的方法和装置。 一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。 还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。 第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。 第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

公开(公告)号：US07535275B1

公开(公告)日：2009-05-19

申请号：US11789598

申请日：2007-04-24

申请人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

发明人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

IPC分类号： H03L7/00

CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0805

摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

摘要翻译： 可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。 然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置，以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

公开(公告)号：US07492185B1

公开(公告)日：2009-02-17

申请号：US11956182

申请日：2007-12-13

申请人： Joseph Huang ,  Chiakang Sung ,  Michael H. M. Chu ,  Yan Chong

发明人： Joseph Huang ,  Chiakang Sung ,  Michael H. M. Chu ,  Yan Chong

IPC分类号： H03K19/173

CPC分类号： H03K19/17744

摘要： The amount of simultaneous switching noise generated through the operation of a programmable device can be reduced by reducing the number of pins switching at the same time. An I/O bank can include a number of I/O pin subsets, or DQS groups, each programmed to switch at a different time so that the switching times of the various pins can be staggered for each system clock cycle. Programmable delay elements can be used to control the delay of each subset. The programmable elements can be placed between the system clock and the output registers in order to delay the receiving of the clock signal by the registers and therefore delaying the switching of the output buffers. The programmable delay elements also can be placed between the output registers and the output buffers in order to delay the receiving of the output data by, and subsequent switching of, the output buffers.

摘要翻译： 通过可编程器件的操作产生的同时开关噪声的量可以通过减少引脚数目同时减少。 I / O bank可以包括多个I / O引脚子集或DQS组，每组都被编程为在不同的时间切换，使得各个引脚的切换时间可以在每个系统时钟周期内交错。 可编程延迟元件可用于控制每个子集的延迟。 可编程元件可以放置在系统时钟和输出寄存器之间，以便延迟寄存器对时钟信号的接收，从而延迟输出缓冲器的切换。 可编程延迟元件也可以放置在输出寄存器和输出缓冲器之间，以便延迟输出缓冲器的输出数据的接收和随后的切换。

公开(公告)号：US07477074B1

公开(公告)日：2009-01-13

申请号：US11609249

申请日：2006-12-11

申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/017581 ,  H03K19/17744

摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

公开(公告)号：US20070282555A1

公开(公告)日：2007-12-06

申请号：US11735386

申请日：2007-04-13

申请人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

发明人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

IPC分类号： G01R35/00

CPC分类号： G01R31/31922 ,  G01R31/3191 ,  G01R31/31937 ,  H04L7/0008 ,  H04L7/0041

摘要： Circuits, methods and apparatus are provided to reduce skew among signals being received by a data interface. Signal path delays are varied such that data and strobe signals received at a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration circuitry provides skew adjustment of each data signal path by determining one or more delays in each data signal path and strobe signal path based on relative timings of test signals. The rising or falling edges may be used for this alignment.

摘要翻译： 提供电路，方法和装置以减少由数据接口接收的信号之间的偏差。 变化信号路径延迟使得在存储器接口处接收的数据和选通信号沿着上升沿和/或下降沿彼此校准或对齐。 例如，自校准电路通过基于测试信号的相对定时确定每个数据信号路径和选通信号路径中的一个或多个延迟来提供每个数据信号路径的偏移调整。 上升或下降沿可用于此对齐。

公开(公告)号：US20070277071A1

公开(公告)日：2007-11-29

申请号：US11735394

申请日：2007-04-13

申请人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

发明人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F13/4213

摘要： Circuits, methods and apparatus are provided to reduce skew among signals being provided or transmitted by a data interface. Signal path delays are varied such that signals transmitted by a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration, external circuitry, or design tools can provide skew adjustment of each output channel by determining one or more delays for each output channel path. When aligning multiple edges, the edges of the output signals may be aligned independently, e.g., using edge specific delay elements.

摘要翻译： 提供电路，方法和装置以减少由数据接口提供或发送的信号之间的偏差。 信号路径延迟是变化的，使得由存储器接口发送的信号沿着上升沿和/或下降沿彼此校准或对齐。 例如，自校准，外部电路或设计工具可以通过确定每个输出通道路径的一个或多个延迟来提供每个输出通道的偏移调整。 当对准多个边缘时，输出信号的边缘可以独立对准，例如使用边缘特定的延迟元件。

公开(公告)号：US07231536B1

公开(公告)日：2007-06-12

申请号：US10799408

申请日：2004-03-12

申请人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Philip Pan

发明人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Philip Pan

IPC分类号： G06F1/12 ,  G06F13/42 ,  G06F1/04

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/108 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091

摘要： Circuits, methods, and apparatus that prevent control signals from changing state while the control signals are being used to delay a read strobe signal. An exemplary embodiment of the present invention provides a control circuit that provides a plurality of control bits to a delay line, where the delay line delays or phase shifts a read strobe signal a duration, where the duration depends on the state of the control bits. The delayed read strobe signal is used to clock one or more data registers. To avoid undesired changes in the duration that the read strobe signal is delayed, the control bits are retimed before being provided to the delay line. A specific embodiment waits for an edge of the strobe signal to be output by the delay line before providing the control bits to the delay line. Another specific embodiment waits until no edge of the strobe signal is being delayed by the delay line before providing the control bits to the delay line.

摘要翻译： 当控制信号被用于延迟读选通信号时，防止控制信号改变状态的电路，方法和装置。 本发明的示例性实施例提供了一种控制电路，其向延迟线提供多个控制位，其中延迟线将读选通信号延迟或相移一段持续时间，其中持续时间取决于控制位的状态。 延迟读选通信号用于对一个或多个数据寄存器进行定时。 为了避免读取选通信号延迟的持续时间的不期望的改变，控制位在提供给延迟线之前重新定时。 特定实施例在将延迟线提供给控制位之前等待延迟线输出选通信号的边沿。 另一个具体实施例等待直到在将延迟线提供给延迟线之前，选通信号的边沿不被延迟线延迟。

公开(公告)号：US07212054B1

公开(公告)日：2007-05-01

申请号：US11479660

申请日：2006-06-29

申请人： Tzung-chin Chang ,  Chiakang Sung ,  Yan Chong ,  Henry Kim ,  Joseph Huang

发明人： Tzung-chin Chang ,  Chiakang Sung ,  Yan Chong ,  Henry Kim ,  Joseph Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector and an up down counter that provides a main control signal to adjust the delay by the main variable delay circuit. When the DLL circuit is locked, an arithmetic logic unit (ALU) produces a processed control signal based on the main control signal, an ALU control signal and an offset control signal, and the processed control signal is provided to the smaller variable delay circuit. By adjusting the ALU control and offset control signals, the phase shift introduced on the DLL control signal by the smaller variable delay circuit can be adjusted. In another embodiment of the invention, a second up down counter is used in place of an ALU for providing a dynamically adjustable phase shift in accordance with the principles of the present invention.

摘要翻译： 描述了用于使用处理的控制信号产生具有可调相移的DLL时钟信号的电路和方法。 在本发明的一个实施例中，提供一种DLL电路，其包括主要和较小的可变延迟电路，相位检测器和向上计数器，其提供主控制信号以通过主可变延迟电路来调整延迟。 当DLL电路被锁定时，算术逻辑单元（ALU）基于主控制信号，ALU控制信号和偏移控制信号产生处理的控制信号，并且处理的控制信号被提供给较小的可变延迟电路。 通过调整ALU控制和偏移控制信号，可以调整由较小的可变延迟电路引入到DLL控制信号上的相移。 在本发明的另一实施例中，根据本发明的原理，使用第二向上计数器来代替ALU来提供动态可调的相移。

公开(公告)号：US07205806B2

公开(公告)日：2007-04-17

申请号：US11181366

申请日：2005-07-13

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

IPC分类号： H03K5/13 ,  H03D3/24

CPC分类号： H03L7/0814 ,  H03L7/085 ,  H03L7/093

摘要： Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.

摘要翻译： 提供了用于环路电路（即DLL电路和PLL电路）的相位比较器。 相位比较器包括用于比较参考时钟信号和从产生的环路电路生成的内部时钟信号导出的反馈信号的相位检测器。 相位比较器还包括低通噪声滤波器，用于通过在环路电路的补偿电路之前需要一定的净数量的前导或滞后检测来滤除参考时钟信号和反馈信号之间的错误检测的相位差（即， 调节DLL电路中的受控延迟线或PLL电路中的受控振荡器）。 在进行这些调整之前所需的净测量数取决于提供给相位比较器的可编程带宽信号。

公开(公告)号：US20060164139A1

公开(公告)日：2006-07-27

申请号：US11181366

申请日：2005-07-13

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Tzung-chin Chang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/085 ,  H03L7/093

摘要： Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.