公开(公告)号：US5237434A

公开(公告)日：1993-08-17

申请号：US787938

申请日：1991-11-05

申请人： Michael R. Feldman ,  Iwona Turlik ,  Gretchen M. Adema

发明人： Michael R. Feldman ,  Iwona Turlik ,  Gretchen M. Adema

IPC分类号： G02B6/10 ,  G02B6/42 ,  G02B6/43 ,  H01L23/48

CPC分类号： H01L24/73 ,  G02B6/43 ,  H01L23/48 ,  G02B6/4232 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15192

摘要： A multichip module having high density optical and electrical interconnections between integrated circuit chips. An optically transparent substrate is positioned overlying an array of integrated circuit chips mounted on a mounting substrate. The mounting substrate may include a heat sink to remove excess heat from the integrated circuit chips. The multichip module includes integrated circuit chips having optical detectors and optical transmitters to establish optical interconnections therebetween. A hologram is positioned in the optical path between the optical transmitters and the optical detectors. A planar mirror is preferably positioned opposite the hologram to direct the optical beams. The optically transparent substrate also includes an array of electrical contact pads to establish electrical connections with corresponding electrical contact pads on the underlying integrated circuit chips. A pattern of electrical interconnection lines is provided on at least one of the mounting substrate or the transparent substrate to electrically interconnect predetermined ones of the integrated circuit chips.

摘要翻译： 集成电路芯片之间具有高密度光电互连的多芯片模块。 光学透明基板定位在安装在安装基板上的集成电路芯片的阵列上。 安装基板可以包括散热器以从集成电路芯片去除多余的热量。 多芯片模块包括具有光学检测器和光发射器的集成电路芯片，以在它们之间建立光学互连。 全息图位于光发射器和光学检测器之间的光路中。 平面镜优选地与全息图相对定位以引导光束。 光学透明基板还包括电接触焊盘的阵列，以与底层集成电路芯片上的对应电接触焊盘建立电连接。 电连接线的图案设置在安装基板或透明基板的至少一个上，以将预定的集成电路芯片电互连。

公开(公告)号：US5206557A

公开(公告)日：1993-04-27

申请号：US619183

申请日：1990-11-27

申请人： Stephen M. Bobbio

发明人： Stephen M. Bobbio

IPC分类号： B06B1/02 ,  H02N1/00 ,  H04R19/00

CPC分类号： H02N1/008 ,  B06B1/0292 ,  H04R19/00

摘要： A microelectromechanical transducer including a plurality of strips arranged in an array and maintained in a closely spaced relation by a plurality of spacers. An electrically conductive layer on portions of the strips and spacers distributes electrical signal within the transducer to cause adjacent portions of the strips to move together. The strips and spacers may be formed from a common dielectric layer using microelectronic fabrication techniques. Two transducers may be coupled at an angle offset from parallel for two-dimensional micropositioning. A photodetector and Fresnel lens may be combined with the micropositioner using the transducers for optical scanning microscopy.

摘要翻译： 一种微电子换能器，包括以阵列排列并由多个间隔物保持紧密间隔的多个条。 条带和间隔物的部分上的导电层在换能器内分布电信号，以使条带的相邻部分一起移动。 条带和间隔物可以由使用微电子制造技术的公共介电层形成。 两个换能器可以以与平行偏移的角度耦合以进行二维微定位。 光电检测器和菲涅尔透镜可以使用光学扫描显微镜的换能器与微型定位器组合。

公开(公告)号：US5145303A

公开(公告)日：1992-09-08

申请号：US662236

申请日：1991-02-28

申请人： John R. Clarke

发明人： John R. Clarke

IPC分类号： H01L21/00 ,  H01L21/677

CPC分类号： H01L21/67754 ,  H01L21/67126 ,  Y10S414/139

摘要： A load lock removes particulate contamination during microelectronic manufacturing. The load lock may have a single door or two doors, or a single door and a funnel valve. A passageway is defined through the load lock when the door or doors, or the funnel valve, are opened. The particulate contamination is removed from the load lock by providing a laminar flow of gas through the passageway. The source for generating the laminar flow may be external to the load lock or internal to the load lock.

摘要翻译： 加载锁定可以在微电子制造过程中消除微粒污染。 装载锁可以具有单个门或两个门，或单个门和漏斗阀。 当门或门或漏斗阀打开时，通过装载锁定定义通道。 通过提供通过通道的气流层流，从负载锁中除去颗粒污染物。 用于产生层流的源可以在负载锁定的外部或负载锁的内部。

公开(公告)号：US5126287A

公开(公告)日：1992-06-30

申请号：US534711

申请日：1990-06-07

申请人： Gary W. Jones

发明人： Gary W. Jones

IPC分类号： H01J9/02

CPC分类号： H01J9/025 ,  H01J2209/0226

摘要： A method of fabricating electron field emitters is disclosed. In this method, a semiconductor substrate is provided with at least one set of alternating conductor and insulator layers formed thereon. An etch is then performed through the at least one set of alternating conductor and insulator layers to form an aperture. An etch resistant layer is formed on the area exposed from the previous etch at the base of the aperture. An etch is performed forming the electron emitter in the one face aligned to the exposed area. The emitter is thereby self-aligned to the overlying conductor and insulator layers. The conductor and insulator layers need not be aligned to an underlying emitter.

摘要翻译： 公开了一种制造电子场发射器的方法。 在该方法中，半导体衬底设置有形成在其上的交替导体和绝缘体层中的至少一组。 然后通过至少一组交替的导体和绝缘体层进行蚀刻以形成孔。 在孔的底部从先前蚀刻暴露的区域上形成耐蚀刻层。 在与暴露区域对准的一个面中进行形成电子发射体的蚀刻。 因此发射极与上覆的导体和绝缘体层自对准。 导体和绝缘体层不必与底层发射体对准。

公开(公告)号：US5039625A

公开(公告)日：1991-08-13

申请号：US516246

申请日：1990-04-27

申请人： Arnold Reisman ,  Mark Kellam ,  Charles K. Williams ,  Nandini Tandon

发明人： Arnold Reisman ,  Mark Kellam ,  Charles K. Williams ,  Nandini Tandon

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L21/823481 ,  H01L21/32 ,  H01L21/76202 ,  Y10S148/086 ,  Y10S148/117

摘要： A Maximum Areal Density Recessed Oxide Isolation (MADROX) process for forming semiconductor devices, in which forms an insulating layer is formed on a monocrystalline silicon substrate and a patterned polycrystalline silicon-containing layer is formed on the insulating layer. The substrate is then subjected to a low temperature plasma assisted oxidation to form recessed oxide isolation areas in the exposed regions of the substrate, with minimal encroachment under the patterned polycrystalline silicon-containing layer. The patterned polycrystalline silicon-containing layer acts as a mask, without itself being oxidized. Low temperature recessed oxide isolation regions may thereby be formed, without "bird's beak" formation. Maximum Areal Density Bipolar and Field Effect Transistor (MADFET) devices may be formed, using the patterned polycrystalline silicon-containing layer as a device contact if desired.

摘要翻译： 在绝缘层上形成最大面积密度的嵌入式氧化物隔离（MADROX）用于形成半导体器件的工艺，其中形成绝缘层，形成在单晶硅衬底和图案化多晶含硅层上。 然后将衬底经受低温等离子体辅助氧化，以在衬底的暴露区域中形成凹陷的氧化物隔离区域，在图案化多晶含硅层下的最小侵蚀。 图案化多晶含硅层用作掩模，其本身不被氧化。 从而可以形成低温凹陷氧化物隔离区，而不会形成“鸟嘴”。 如果需要，可以使用图案化多晶硅层作为器件接触来形成最大面密度双极场效应晶体管（MADFET）器件。

公开(公告)号：US5001082A

公开(公告)日：1991-03-19

申请号：US337187

申请日：1989-04-12

申请人： Scott H. Goodwin-Johansson

发明人： Scott H. Goodwin-Johansson

IPC分类号： H01L21/285 ,  H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/665 ,  Y10S148/019 ,  Y10S148/116

摘要： A self-aligned salicide process produces small dimensioned semiconductor devices, for example metal oxide semiconductor (MOS) devices. An electrode is formed on the face of a semiconductor substrate, the electrode having a top and a sidewall and an insulating coating on the sidewall. Then a silicon layer and a refractory metal layer are formed on the face, top and sidewall, with one of the layers being continuous, and the other layer having a break on the sidewall. In a preferred embodiment the silicon layer is directionally applied, to form thick portions on the face and top and thin portion on the sidewall. The thin portion on the sidewall is removed and a metal layer is uniformly deposited. The substrate is heated to convert at least part of the silicon and metal layers to silicide. The silicide layer on the face is planar and does not consume the substrate at the face, allowing shallow source and drain regions to be formed.

摘要翻译： 自对准的自对准硅化物工艺生产小尺寸的半导体器件，例如金属氧化物半导体（MOS）器件。 电极形成在半导体衬底的表面上，电极具有顶部和侧壁以及侧壁上的绝缘涂层。 然后在表面，顶部和侧壁上形成硅层和难熔金属层，其中一层是连续的，另一层在侧壁上具有断裂。 在优选实施例中，硅层被定向地施加，以在侧壁上的表面和顶部以及薄的部分上形成厚的部分。 去除侧壁上的薄部分并均匀地沉积金属层。 将衬底加热以将至少部分硅和金属层转化为硅化物。 表面上的硅化物层是平面的，并且不消耗基板在表面，允许形成浅的源极和漏极区域。

公开(公告)号：US20060238067A1

公开(公告)日：2006-10-26

申请号：US11068776

申请日：2005-03-02

申请人： David Dausch

发明人： David Dausch

IPC分类号： H01L41/00

CPC分类号： B06B1/0622 ,  A61B8/4483

摘要： A piezoelectric micromachined ultrasonic transducer comprising a substrate and a first dielectric film formed on the substrate. An opening having a sidewall is formed through the substrate and first dielectric film. A bottom electrode is formed on the first dielectric film spanning the opening. A piezoelectric element is formed on the bottom electrode. A second dielectric film surrounds the piezoelectric element. A conformal insulating film is formed on the sidewall of the opening. A conformal conductive film is formed in contact with the bottom electrode and on the sidewall of the opening, wherein an open cavity is maintained in the opening. A top electrode is formed in contact with the piezoelectric element.

摘要翻译： 一种压电微机械超声波换能器，包括基板和形成在基板上的第一电介质膜。 具有侧壁的开口通过基板和第一介电膜形成。 底部电极形成在跨越开口的第一电介质膜上。 在底部电极上形成压电元件。 第二电介质膜围绕压电元件。 在开口的侧壁上形成保形绝缘膜。 形成与底部电极和开口的侧壁接触的保形导电膜，其中在开口中保持开口腔。 顶部电极形成为与压电元件接触。

公开(公告)号：US20050013613A1

公开(公告)日：2005-01-20

申请号：US10849204

申请日：2004-05-20

申请人： Daniel Stevenson ,  Mark Cassada ,  Pronita Mehrotra

发明人： Daniel Stevenson ,  Mark Cassada ,  Pronita Mehrotra

IPC分类号： H04B10/20 ,  H04Q11/00

CPC分类号： H04Q11/0066 ,  H04Q2011/0064 ,  H04Q2011/0088

摘要： Optical burst switch network system and method with Just-in-Time (JIT) signaling and advanced data transmission and memory access and management. The system and method allow concurrent data transmission having arbitrary signal types, such as analog and digital signal types, in which the JIT signaling allows for subsequent simultaneous transmission of optical signals that do not require electro-optical conversion. The system includes an optical signal bus having a passive star coupler. A plurality of network adapters that are in optical communication with the optical signal bus and in network communication with network terminal devices are provided. The network adapters include receivers, transmitters and control logic that allows for bi-directional movement of data signals as bursts between the terminal equipment and the network system. The transmitter and receiver may be fixed or tunable. The system further includes an optical bus controller in optical communication with the optical signal bus that processes signals from the optical signal bus to connect a requested network adapter to a requesting network adapter in accordance with the user-to-network protocol. The network system implements a just-in-time signaling protocol to signal nodes in the network that burst communications are forthcoming. Optionally, the system allows comprehensive memory access in a Local Area Network (LAN). The nodes in the network are capable of seamlessly addressing memories of all other nodes that comprise the network.

摘要翻译： 光突发交换机网络系统及方法，具有即时（JIT）信令和高级数据传输和存储器访问和管理。 该系统和方法允许具有任意信号类型（例如模拟和数字信号类型）的并发数据传输，其中JIT信令允许随后同时传输不需要电光转换的光信号。 该系统包括具有无源星形耦合器的光信号总线。 提供了与光信号总线光通信并与网络终端设备进行网络通信的多个网络适配器。 网络适​​配器包括接收机，发射机和控制逻辑，其允许数据信号作为终端设备和网络系统之间的突发的双向移动。 发射机和接收机可以是固定的或可调谐的。 该系统还包括与光信号总线光通信的光总线控制器，其处理来自光信号总线的信号，以根据用户到网络协议将请求的网络适配器连接到请求的网络适配器。 网络系统实现即时信令协议，以向网络中的信令节点突发通信即将到来。 可选地，系统允许在局域网（LAN）中进行全面的存储器访问。 网络中的节点能够无缝地寻址构成网络的所有其他节点的存储器。

公开(公告)号：US20040201095A1

公开(公告)日：2004-10-14

申请号：US10834224

申请日：2004-04-29

申请人： MCNC

发明人： William Devereux Palmer ,  Salvature Bonafede ,  Dorota Temple ,  Brian Stoner

IPC分类号： H01L023/053

CPC分类号： H05K3/0055 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01S5/02 ,  H01S5/0207 ,  H01S5/02272 ,  H01S5/042 ,  H01S5/423 ,  H05K1/0306 ,  H05K2201/0179 ,  H05K2201/09581 ,  H01L2924/014

摘要： An improved through-via vertical interconnect, through-via heat sinks and associated fabrication techniques are provided for. The devices benefit from an organic dielectric layer that allows for low-temperature deposition processing. The low-temperature processing used to form the through-via interconnects and heat sinks allows for the formation of the interconnects and heat sinks at any point in the fabrication of the semiconductor device, including post-formation of active devices and associated circuitry. The through-via vertical interconnects of the present invention are fabricated so as to insure conformal thickness of the various layers that form the interconnect constructs. As such, the interconnects can be formed with a high aspect ratio, in the range of about 4:1 to about 10:1, substrate thickness to interconnect diameter.

摘要翻译： 提供改进的通孔垂直互连，通孔散热器和相关的制造技术。 这些器件受益于允许进行低温沉积处理的有机介电层。 用于形成通孔互连和散热器的低温处理允许在半导体器件的制造中的任何点处形成互连和散热器，包括有源器件和相关电路的形成。 制造本发明的通孔垂直互连件以确保形成互连结构的各种层的适形厚度。 因此，互连可以以约4:1至约10:1的高纵横比形成，使基板厚度互连直径。

公开(公告)号：US20040124943A1

公开(公告)日：2004-07-01

申请号：US10334985

申请日：2002-12-31

申请人： MCNC

发明人： Mark W. Roberson ,  Philip A. Deane ,  Charles Kenneth Williams

IPC分类号： H03H005/00 ,  G02B006/26

CPC分类号： H01P5/185 ,  H01P5/187

摘要： Three dimensional electronic and optical coupling devices that are capable of providing high speed coupling over a large frequency range while limiting the amount of space consumption in the communications network. An optical or electrical coupling device comprises a first substrate and a second substrate adjacent to the first substrate having one or more optical waveguides or microstrips formed thereon. The substrates will have disposed thereon conductive microstrips and/or dielectric elements. The one or more optical waveguides or microstrips formed on the first substrate correspond to at least one optical waveguides or microstrips formed on the second substrate so as to facilitate optical coupling between the corresponding waveguides. Precise spacing between the substrates and precise spacing between the optical waveguides or microstrips facilitate the requisite optical/RF coupling.

摘要翻译： 三维电子和光耦合器件能够在大的频率范围内提供高速耦合，同时限制通信网络中的空间消耗量。 光学或电耦合装置包括第一衬底和与第一衬底相邻的第二衬底，其具有在其上形成的一个或多个光波导或微带。 衬底将布置在其上导电微带和/或电介质元件。 形成在第一基板上的一个或多个光波导或微带对应于形成在第二基板上的至少一个光波导或微带，以便于相应波导之间的光耦合。 基板之间的精确间隔和光波导或微带之间的精确间隔有助于所需的光/ RF耦合。