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51.发明申请Systems and Methods for Choosing a Memory Block for the Storage of Data Based on a Frequency With Which the Data is Updated 审中-公开基于数据更新频率的数据存储选择存储器块的系统和方法公开(公告)号：US20160188455A1
公开(公告)日：2016-06-30
申请号：US14584388
申请日：2014-12-29
发明人： Leena Patel
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1044 , G06F2212/7202 , G06F2212/7204
摘要： Systems and methods for choosing a memory block for the storage of data based on a frequency with which data is updated are disclosed. In one implementation, a memory management module of a non-volatile memory system receives a request to open a free memory block for the storage of data. The memory management module determines a frequency with which the data is updated. The memory management module then opens a memory block of a first portion a free block list that is associated with low program/erase cycle counts in response to determining that the data will be frequently updated or opens a memory block of a second different portion of the free block list that is associated with high program/erase cycle counts in response to determining that the data is not frequently updated. The memory management module then stores the data in the open memory block of the non-volatile memory.
摘要翻译： 公开了用于基于更新数据的频率来选择用于存储数据的存储器块的系统和方法。 在一个实现中，非易失性存储器系统的存储器管理模块接收打开用于存储数据的空闲存储器块的请求。 存储器管理模块确定数据被更新的频率。 然后，存储器管理模块响应于确定数据将被频繁地更新或者打开第二部分的存储器块，打开第一部分的存储块，该自由块列表与低编程/擦除周期计数相关联 响应于确定数据不被频繁更新而与高编程/擦除周期计数相关联的空闲块列表。 存储器管理模块然后将数据存储在非易失性存储器的开放存储器块中。
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52.发明申请公开(公告)号：US20160188401A1
公开(公告)日：2016-06-30
申请号：US14584825
申请日：2014-12-29
发明人： Zhenlei Shen , Xinde Hu , Lei Chen , Yiwei Song
IPC分类号： G06F11/07
CPC分类号： G06F11/0751 , G06F11/0703 , G06F11/073
摘要： Systems and methods for controlling blocks in a memory device using a health indicator (such as the failed bit count) for the blocks are disclosed. However, the health indicator may exhibit noise, thereby resulting in an unreliable indicator of the health of the blocks in the memory device. In order to filter out the noise, a rolling average of the health indicator may be determined, and compared to the current health indicator. The comparison with the rolling average may indicate whether the current health indicator is an outlier, and thus should not be used. The health indicator may also be used to predict a future health indicator for different blocks in the memory device. Using the predicted future health indicator, the use of the blocks may be changed in order to more evenly wear the blocks.
摘要翻译： 公开了用于使用健康指示器（诸如故障位计数）来控制块的存储器件中的块的系统和方法。 然而，健康指示器可能表现出噪音，从而导致存储器装置中块的健康状况的不可靠指示。 为了滤除噪声，可以确定健康指标的滚动平均值，并与当前健康指标进行比较。 与滚动平均值的比较可以指示当前健康指标是否是离群值，因此不应该使用。 健康指示器还可以用于预测存储器设备中不同块的未来健康指示符。 使用预测的未来健康指示器，可以改变块的使用以便更均匀地佩戴块。
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53.发明授权公开(公告)号：US09379124B2
公开(公告)日：2016-06-28
申请号：US14314370
申请日：2014-06-25
发明人： Rahul Sharangpani , Raghuveer S. Makala , Thomas Jongwan Kwon , Senaka Kanakamedala , George Matamis
IPC分类号： G11C11/34 , H01L27/115 , H01L29/423 , G11C16/04 , G11C16/06 , H01L29/788 , H01L21/28 , H01L21/285 , H01L21/311 , H01L21/3205 , H01L21/02
CPC分类号： H01L27/11556 , G11C16/0408 , G11C16/06 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/28273 , H01L21/28556 , H01L21/28562 , H01L21/28568 , H01L21/31111 , H01L21/32055 , H01L27/11519 , H01L27/11524 , H01L29/42332 , H01L29/7883
摘要： A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide.
摘要翻译： 包括半导体通道和多个控制栅电极的单片三维NAND串的制造方法包括使用原子层沉积选择性地形成多个离散的电荷存储区域。 多个离散电荷存储区域包括金属或导电金属氧化物中的至少一种。
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公开(公告)号：US09379120B2
公开(公告)日：2016-06-28
申请号：US13947530
申请日：2013-07-22
发明人： Vinod Robert Purayath , Tuan Pham , Hiroyuki Kinoshita , Yuan Zhang , Henry Chin , James K Kai , Takashi W Orimoto , George Matamis , Henry Chien
IPC分类号： H01L29/788 , H01L27/115 , H01L21/28 , H01L21/764 , H01L21/768 , H01L29/66
CPC分类号： H01L27/11517 , H01L21/28273 , H01L21/764 , H01L21/7682 , H01L27/11519 , H01L27/11521 , H01L29/66825
摘要： High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.
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公开(公告)号：US20160180959A1
公开(公告)日：2016-06-23
申请号：US14977155
申请日：2015-12-21
CPC分类号： G06F3/0653 , G06F3/0625 , G06F3/0634 , G06F11/008 , G06F11/073 , G06F11/076 , G06F11/079 , G06F11/0793 , G11C11/5628 , G11C16/0483 , G11C16/12 , G11C16/28 , G11C16/32 , G11C16/3418 , G11C16/3422 , G11C16/349 , G11C16/3495 , G11C29/028 , G11C29/50004 , G11C29/52 , G11C29/56008 , G11C29/70 , G11C2029/5004
摘要： A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.
摘要翻译： 存储器系统或闪存卡可以包括用于存储器单元测量和分析的机制，其独立地测量/预测存储器磨损/耐久性，数据保持（DR），读取干扰和/或剩余余量。 可以通过分析单元的各个电压电平的状态分布来独立地量化这些效应。 特别地，可以分析存储器单元的单元电压分布的直方图以识别特定效果的签名（例如，磨损，DR，读取干扰，余量等）。 这些测量可用于块循环，数据丢失预测或对存储器参数的调整。 在适当的时间基于测量的优先行动可能会导致改进的内存管理和数据管理。 该动作可以包括计算存储在存储器中的数据的剩余使用寿命，循环块，预测数据丢失，权衡或动态调整存储器参数。
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56.发明申请公开(公告)号：US20160180953A1
公开(公告)日：2016-06-23
申请号：US14977191
申请日：2015-12-21
IPC分类号： G11C16/34
CPC分类号： G06F3/0653 , G06F3/0625 , G06F3/0634 , G06F11/008 , G06F11/073 , G06F11/076 , G06F11/079 , G06F11/0793 , G11C11/5628 , G11C16/0483 , G11C16/12 , G11C16/28 , G11C16/32 , G11C16/3418 , G11C16/3422 , G11C16/349 , G11C16/3495 , G11C29/028 , G11C29/50004 , G11C29/52 , G11C29/56008 , G11C29/70 , G11C2029/5004
摘要： A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.
摘要翻译： 存储器系统或闪存卡可以包括用于存储器单元测量和分析的机制，其独立地测量/预测存储器磨损/耐久性，数据保持（DR），读取干扰和/或剩余余量。 可以通过分析单元的各个电压电平的状态分布来独立地量化这些效应。 特别地，可以分析存储器单元的单元电压分布的直方图以识别特定效果的签名（例如，磨损，DR，读取干扰，余量等）。 这些测量可用于块循环，数据丢失预测或对存储器参数的调整。 在适当的时间基于测量的优先行动可能会导致改进的内存管理和数据管理。 该动作可以包括计算存储在存储器中的数据的剩余使用寿命，循环块，预测数据丢失，权衡或动态调整存储器参数。
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公开(公告)号：US20160179602A1
公开(公告)日：2016-06-23
申请号：US14977198
申请日：2015-12-21
CPC分类号： G06F3/0653 , G06F3/0625 , G06F3/0634 , G06F11/008 , G06F11/073 , G06F11/076 , G06F11/079 , G06F11/0793 , G11C11/5628 , G11C16/0483 , G11C16/12 , G11C16/28 , G11C16/32 , G11C16/3418 , G11C16/3422 , G11C16/349 , G11C16/3495 , G11C29/028 , G11C29/50004 , G11C29/52 , G11C29/56008 , G11C29/70 , G11C2029/5004
摘要： A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.
摘要翻译： 存储器系统或闪存卡可以包括用于存储器单元测量和分析的机制，其独立地测量/预测存储器磨损/耐久性，数据保持（DR），读取干扰和/或剩余余量。 可以通过分析单元的各个电压电平的状态分布来独立地量化这些效应。 特别地，可以分析存储器单元的单元电压分布的直方图以识别特定效果的签名（例如，磨损，DR，读取干扰，余量等）。 这些测量可用于块循环，数据丢失预测或对存储器参数的调整。 在适当的时间基于测量的优先行动可能会导致改进的内存管理和数据管理。 该动作可以包括计算存储在存储器中的数据的剩余使用寿命，循环块，预测数据丢失，权衡或动态调整存储器参数。
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公开(公告)号：US09372632B2
公开(公告)日：2016-06-21
申请号：US14635840
申请日：2015-03-02
发明人： Paul A. Lassa
CPC分类号： G06F3/0619 , G06F3/061 , G06F3/0626 , G06F3/0653 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F9/30101
摘要： The embodiments described herein provide a controller with an extended status register and a method of use therewith. In one embodiment, a controller is provided with a first interface through which to communicate with a host and a second interface through which to communicate with a plurality of flash memory devices. The controller also comprises a status register, an extended status register, and a processor. The processor is operative to store, in the extended status register, status information of a plurality of events in time across the plurality of flash memory devices. The extended status register stores event status information, whereas the ONFI status register stores command status information. In response to a request from the host, the processor sends the status information of the plurality of events to the host for analysis.
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公开(公告)号：US09368224B2
公开(公告)日：2016-06-14
申请号：US14175196
申请日：2014-02-07
发明人： Sung-En Wang , Jonathan Huynh , Steve Choi , Jongmin Park
CPC分类号： G11C16/28 , G11C16/0483 , G11C16/24 , G11C16/26
摘要： To maintain stability of memory array operations, a supplemental current can supply a common source line of a memory array so that the combined current from the memory array and supplemental current is at least a minimum regulation current level. When enabled for sensing operations, a driver circuit maintains the common source line's voltage level. A current subtractor circuit determines the difference between a reference current and a current proportional to the current flowing from the array, where the reference current is proportional to the minimum regulation current. The difference current is then mirrored by a self-adjusting current loop and supplied to the common source line to maintain its current level.
摘要翻译： 为了保持存储器阵列操作的稳定性，补充电流可以提供存储器阵列的公共源极线，使得来自存储器阵列和补充电流的组合电流至少为最小调节电流电平。 当启用感测操作时，驱动电路保持公共源极线的电压电平。 电流减法器电路确定参考电流和与从阵列流动的电流成比例的电流之间的差异，其中参考电流与最小调节电流成比例。 然后，差分电流由自调节电流回路镜像并提供给公共源极线以保持其当前电平。
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公开(公告)号：US20160162357A1
公开(公告)日：2016-06-09
申请号：US14657677
申请日：2015-03-13
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1048 , G11C29/42 , G11C29/52 , G11C2029/0411
摘要： Devices and methods implemented therein in are disclosed for correcting errors in data. The method comprises determining that a first copy of data and a second copy of data include errors uncorrectable by an error correction code (ECC) engine. The ECC engine is modified based on determining that the first copy of data and the second copy of data include errors uncorrectable by the ECC engine and using the modified ECC engine, the first copy of data and the second copy of data are processed to correct the errors in the first and second copy of the data.
摘要翻译： 公开了其中实现的装置和方法，用于纠正数据中的错误。 该方法包括确定数据的第一副本和数据的第二副本包括由纠错码（ECC）引擎不可校正的错误。 基于确定数据的第一副本和数据的第二副本包括由ECC引擎不可校正的错误并使用修改的ECC引擎来修改ECC引擎，处理数据的第一副本和数据的第二副本以校正 第一个和第二个数据副本中的错误。
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