公开(公告)号：US08441878B2

公开(公告)日：2013-05-14

申请号：US13490700

申请日：2012-06-07

Applicant: Richard C. Foss

Inventor： Richard C. Foss

IPC: G11C7/02

CPC classification number: G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

Abstract: A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors.

Abstract translation: 具有位线对的动态随机存取存储器（DRAM），每对都连接到第一位线读出放大器，与形成阵列的位线对交叉的字线，连接到位线的电荷存储单元，每个具有连接到位线的使能输入 字线，位线读出放大器以二维阵列连接，成对的初级数据总线通过第一存取晶体管连接到阵列的每一行中的多个相应的位线读出放大器，用于使第一存取晶体管的列，数据总线 每个连接到对应的数据总线对的读出放大器，辅助数据总线，通过第二存取晶体管连接到数据总线读出放大器的次级数据总线，以及用于使能第二存取晶体管的装置。

公开(公告)号：US20130077424A1

公开(公告)日：2013-03-28

申请号：US13625461

申请日：2012-09-24

Applicant: Kensuke Shinohara

Inventor： Kensuke Shinohara

IPC: G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C2207/002 ,  G11C2207/005

Abstract: A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line, and a read control circuit having a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the fourth transistor is brought into conduction on the basis of the input from a charged global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the memory circuits is output to the third bit line.

Abstract translation: 半导体存储器件包括连接到第一位线，第二位线和字线的第一存储器电路，连接到第一预充电控制线的第一预充电控制电路，第一位线和第二位 并且基于来自第一预充电控制线的输入对第一位线和第二位线进行预充电，以及具有第一晶体管，第二晶体管，第三晶体管和第四晶体管的读取控制电路 晶体管，其中基于来自充电的全局位线驱动器控制线的输入使第四晶体管导通，因此选择具有第一位线和第二位线的列，并且将信息保存在 连接到存储器电路中的被驱动字线的存储器电路被输出到第三位线。

公开(公告)号：US20130064021A1

公开(公告)日：2013-03-14

申请号：US13619778

申请日：2012-09-14

Applicant: Francesco La Rosa

Inventor： Francesco La Rosa

IPC: G11C7/06

CPC classification number: G11C16/24 ,  G11C7/12 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/005

Abstract: The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the output of the voltage generator during a first period of the precharge phase, so as to boost the bitline voltage, then for linking the gate terminal to the output of the voltage generator during a second period of the precharge phase. Application in particular to sense amplifiers for non-volatile memories.

Abstract translation: 本发明涉及包括共源共栅晶体管的读出放大器和用于偏置共源共栅晶体管的装置，向共源共栅晶体管的栅极端提供控制电压。 用于偏置共源共栅晶体管的装置包括用于在预充电阶段的第一周期期间将共源共栅晶体管的栅极端子与电压发生器的输出隔离的装置，以便提升位线电压，然后将栅极端子连接到 在预充电阶段的第二周期期间电压发生器的输出。 尤其适用于非易失性存储器的读出放大器。

公开(公告)号：US20120250441A1

公开(公告)日：2012-10-04

申请号：US13077798

申请日：2011-03-31

Applicant: Richard S. Roy ,  Dipak K. Sikdar

Inventor： Richard S. Roy ,  Dipak K. Sikdar

IPC: G11C7/12 ,  G11C7/06

CPC classification number: G11C11/4091 ,  G11C2207/005

Abstract: A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.

Abstract translation: 存储器系统，其包括耦合到第一组动态随机存取存储器（DRAM）单元的第一位线，耦合到第二组DRAM单元的第二（互补）位线以及耦合到第一和第二 位线。 感测放大器包括耦合在第一和第二位线之间的一对交叉耦合的反相器（或类似的锁存电路）以及将第一位线耦合到第一全局位线的第一选择晶体管和第二选择 晶体管将第二位线耦合到第二全局位线。 独立地控制第一和第二选择晶体管，由此能够实现改进的读和写访问序列，从而消除与位线耦合相关联的信号损耗，消除读取凸起条件，并消除后期写入条件。

公开(公告)号：US08279698B2

公开(公告)日：2012-10-02

申请号：US13285445

申请日：2011-10-31

Applicant: Joong-Ho Lee

Inventor： Joong-Ho Lee

IPC: G17C7/02

CPC classification number: G11C11/4097 ,  G11C7/02 ,  G11C7/1066 ,  G11C7/18 ,  G11C2207/005

Abstract: A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.

Abstract translation: 半导体存储器件包括被配置为形成存储单元矩阵并且分别包括第一位线和第二位线的第一和第二子存储器单元区域，以形成对应于预定存储器单元的数据传输路径，附加位线 被配置为跨越第一子存储单元区域并通过与第二位线连接形成数据传送路径;感测和放大单元，被配置为感测和放大通过附加位线和第一位线输入的数据。

公开(公告)号：US08264010B2

公开(公告)日：2012-09-11

申请号：US12830754

申请日：2010-07-06

Applicant: Qiang Tang ,  Ramin Ghodsi

Inventor： Qiang Tang ,  Ramin Ghodsi

IPC: H01L27/118

CPC classification number: G11C7/18 ,  G11C2207/005

Abstract: In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry.

Abstract translation: 在本发明的一个实施例中，用于将多个位线连接到感测电路的方法包括提供从第一金属层中的存储器阵列延伸的多个位线。 多个位线在第一金属层的第一区域中彼此间隔开平均间隔x。 该方法还包括将多个位线的一部分升高到覆盖第一金属层的第二金属层。 升高的位线在第二金属层中以平均间隔y彼此分开，y> x。 该方法还包括将多个位线的一部分延伸到第一金属层的第二区域中。 扩展位线在第一金属层的第二区域中的平均间隔z彼此分开，z> x。 该方法还包括将第二金属层中的位线和第一金属层中的位线连接到感测电路。

公开(公告)号：US08213251B2

公开(公告)日：2012-07-03

申请号：US12829987

申请日：2010-07-02

Applicant: Tae-Sik Yun ,  Kang-Seol Lee

Inventor： Tae-Sik Yun ,  Kang-Seol Lee

IPC: G11C7/02

CPC classification number: G11C11/4091 ,  G11C7/08 ,  G11C7/1048 ,  G11C11/4087 ,  G11C2207/005

Abstract: A semiconductor memory device includes a cell block including a first bit line, a sense amplifier unit including a second bit line and configured to amplify a data signal applied to the second bit line, a connection unit configured to selectively connect the first bit line and the second bit line, a connection control unit configured to receive a control signal for driving the sense amplifier unit and a selection signal for selecting the cell block and generate a connection signal for activating the connection unit at a first time, and a sense amplifier driving control unit configured to receive the control signal and generate a sense amplifier driving signal for driving the sense amplifier unit at a second time after the first time.

Abstract translation: 半导体存储器件包括：包括第一位线的单元块，包括第二位线的读出放大器单元，用于放大施加到第二位线的数据信号;连接单元，被配置为选择性地将第一位线和 第二位线，连接控制单元，被配置为接收用于驱动读出放大器单元的控制信号和用于选择单元块的选择信号，并且在第一时间产生用于激活连接单元的连接信号，以及读出放大器驱动控制 被配置为接收控制信号并且在第一次之后的第二时间产生用于驱动读出放大器单元的读出放大器驱动信号。

公开(公告)号：US20120087200A1

公开(公告)日：2012-04-12

申请号：US13159821

申请日：2011-06-14

Applicant: Sang Hee LEE ,  Jeong Tae HWANG

Inventor： Sang Hee LEE ,  Jeong Tae HWANG

IPC: G11C8/12 ,  G11C8/06

CPC classification number: G11C8/12 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4094 ,  G11C2207/005

Abstract: A semiconductor memory device includes first and second bank groups and an internal column address generating circuit. Each of the first and second bank groups includes at least one bank. The internal column address generating circuit converts a column address into a first internal column address and outputs the first internal column address through a first transmission line in response to a bank address if a read operation or a write operation is performed on a bank of the first bank group. Also, the internal column address generating circuit converts the column address into a second internal column address and outputs the second internal column address through a second transmission line in response to the bank address if a read operation or a write operation is performed on a bank of the second bank group.

Abstract translation: 半导体存储器件包括第一和第二组组以及内部列地址发生电路。 第一和第二银行组中的每一个包括至少一个银行。 内部列地址发生电路将列地址转换为第一内部列地址，并且如果对第一内部列地址的存储体执行读取操作或写入操作，则响应于存储体地址而通过第一传输线输出第一内部列地址 银行集团。 此外，内部列地址发生电路将列地址转换为第二内部列地址，并且如果对一行的行执行读取操作或写入操作，则响应于存储体地址而通过第二传输线输出第二内部列地址 第二银行集团。

公开(公告)号：US20120087169A1

公开(公告)日：2012-04-12

申请号：US12900232

申请日：2010-10-07

Applicant: Harry Kuo ,  Hagop Nazarian

Inventor： Harry Kuo ,  Hagop Nazarian

IPC: G11C7/06 ,  G11C11/21 ,  G11C5/06

CPC classification number: G11C13/0004 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C2207/005 ,  G11C2213/15 ,  G11C2213/78

Abstract: A non-volatile memory device includes a plurality of memory units provided in an array, each memory unit having a plurality of resistive memory cells and a local word line. Each resistive memory units has a first end and a second end, the second ends of the resistive memory cells of each memory unit being coupled to the local word line of the corresponding memory unit. A plurality of bit lines is provided, each bit line being coupled to the first end of one of the resistive memory cells. A plurality of select transistors is provided, each select transistor being assigned to one of the memory units and having a drain terminal coupled to the local word line of the assigned memory unit. First and second global word lines are provided, each global word line being coupled to a control terminal of at least one select transistor. First and second source lines are provided, each source line being coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all of the resistive memory cells in one of the memory units selected for a read operation.

Abstract translation: 非易失性存储器件包括设置在阵列中的多个存储器单元，每个存储器单元具有多个电阻存储器单元和本地字线。 每个电阻式存储器单元具有第一端和第二端，每个存储器单元的电阻性存储单元的第二端耦合到相应的存储器单元的本地字线。 提供多个位线，每个位线耦合到一个电阻存储单元的第一端。 提供多个选择晶体管，每个选择晶体管被分配给存储器单元中的一个并且具有耦合到所分配的存储器单元的本地字线的漏极端子。 提供第一和第二全局字线，每个全局字线耦合到至少一个选择晶体管的控制端。 提供第一和第二源极线，每个源极线耦合到至少一个选择晶体管的源极端子。 存储器件被配置为同时读出为读操作选择的存储器单元之一中的所有电阻存储器单元。

公开(公告)号：US20120075945A1

公开(公告)日：2012-03-29

申请号：US12888748

申请日：2010-09-23

Applicant: Greg M. Hess

Inventor： Greg M. Hess

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C29/846 ,  G11C2207/005 ,  G11C2207/104

Abstract: A dynamic circuit utilizing a passgate on a bit line is disclosed. In one embodiment, a precharge circuit is coupled to a first bit line, while a discharge circuit is coupled to a second bit line. A passgate transistor is coupled between the first bit line and the second bit line. A gate terminal of the passgate transistor may be hardwired or otherwise held to a static voltage such that it remains active when the circuit is operating. During a precharge phase, the precharge circuit may precharge the first bit line to a voltage that is at or near a supply voltage of the circuit. The second bit line may be precharged, through the passgate transistor, responsive to the precharging of the first bit line. The second bit line may be precharged to a voltage that is at least a threshold voltage less than the supply voltage.

Abstract translation: 公开了一种利用位线上的通路的动态电路。 在一个实施例中，预充电电路耦合到第一位线，而放电电路耦合到第二位线。 通路晶体管耦合在第一位线和第二位线之间。 通道晶体管的栅极端子可以是硬连线的或以其它方式被保持为静态电压，使得其在电路工作时保持有效。 在预充电阶段期间，预充电电路可以将第一位线预充电到处于或接近电路的电源电压的电压。 响应于第一位线的预充电，第二位线可以通过通路晶体管被预充电。 第二位线可以被预充电到至少小于电源电压的阈值电压的电压。