公开(公告)号：US09838967B2

公开(公告)日：2017-12-05

申请号：US14595085

申请日：2015-01-12

Applicant: Intel Corporation

Inventor： Jaya L. Jeyaseelan ,  Jim Walsh ,  Robert E. Gough ,  Barnes Cooper ,  Neil W. Songer

IPC: H04W52/02 ,  G06F1/32 ,  H04L12/26

CPC classification number: H04W52/0225 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3296 ,  G06F13/4282 ,  H04L43/0858 ,  Y02D10/151 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/23

Abstract: An apparatus is provided that includes a transceiver to transmit and receive data between an upstream device and the apparatus, and further includes service latency reporting logic coupled to the transceiver to provide a service latency tolerance value of the apparatus to the upstream device, the service latency tolerance value corresponding to an activity state of the apparatus. The service latency tolerance value for an idle activity state can be greater than the service latency tolerance value for an active activity state.

公开(公告)号：US09838286B2

公开(公告)日：2017-12-05

申请号：US14549373

申请日：2014-11-20

Applicant: Telefonaktiebolaget L M Ericsson (publ)

Inventor： Ying Zhang ,  Joel Halpern

IPC: H04L12/26 ,  H04L12/801 ,  H04B1/00 ,  H04B17/00

CPC classification number: H04L43/0829 ,  H04B1/0003 ,  H04B17/00 ,  H04L43/062 ,  H04L43/0835 ,  H04L43/0858 ,  H04L47/12

Abstract: A method is implemented by a computing device to monitor the performance of packet processing in an in-line service chain. The computing device is in communication with a plurality of network devices forming a software defined network (SDN) and the in-line service chain. The SDN includes a controller implemented by the computing device to configure the plurality of network devices. The plurality of devices includes a set of switches monitoring packets traversing the in-line service chain including at least one service.

公开(公告)号：US20170302664A1

公开(公告)日：2017-10-19

申请号：US15457909

申请日：2017-03-13

Applicant: PAYPAL, INC.

Inventor： Rasta A. Mansour ,  Upendra Mardikar

IPC: H04L29/06 ,  H04L12/26 ,  G06F21/44 ,  H04L29/08 ,  G06Q20/20 ,  G06Q20/32

CPC classification number: H04L63/0876 ,  G06F21/34 ,  G06F21/44 ,  G06F21/725 ,  G06F2221/2111 ,  G06F2221/2129 ,  G06F2221/2151 ,  G06Q20/20 ,  G06Q20/3255 ,  G06Q20/3278 ,  G06Q20/40 ,  H04L43/08 ,  H04L43/0858 ,  H04L63/08 ,  H04L67/18

Abstract: Methods and systems for authenticating a user device employ a database of global network latencies categorized and searchable by location and calendar date-time of day usage, providing network latency by geography and by time. The database is constructed using voluminous daily data collected from a world-wide clientele of users who sign in to a particular website. Accuracy of the latency data and clock skew machine identification is made practical and useful for authentications using a service provider-proprietary, stable reference clock, such as an atomic clock, so that internal clock jitter of a service provider performing authentications does not affect the network latency time and clock skew identification of user devices. Increased authentication confidence results from using the database for correcting network latency times and user device signatures generated from the clock skew identifications and for cross checking the authentication using comparisons of initial registration to current sign in data.

公开(公告)号：US20170264557A1

公开(公告)日：2017-09-14

申请号：US15329955

申请日：2014-07-28

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： Wolfgang John ,  Catalin Meirosu

IPC: H04L12/851 ,  H04L12/841 ,  H04L12/721 ,  H04L12/26

CPC classification number: H04L47/2483 ,  H04L41/0206 ,  H04L41/0213 ,  H04L43/026 ,  H04L43/0835 ,  H04L43/0858 ,  H04L43/18 ,  H04L45/38 ,  H04L45/64 ,  H04L47/28 ,  Y02D50/30

Abstract: Mechanisms for devolving microflows from aggregate flows are disclosed. An ingress node receives a packet that matches an aggregate flow entry in a flow table. A determination that a devolve action is associated with the aggregate flow entry is made. Based on the determination that the devolve action is associated with the aggregate flow entry, a microflow flow entry is generated in the flow table to define a microflow. The microflow flow entry includes header information extracted from the packet. Microflow generation information that identifies the microflow is sent to a controller node. It is determined that the microflow has timed out based on an idle timeout period of time. In response to determining that the microflow has timed out, microflow termination information that includes path measurement metric information associated with the microflow is sent to the controller node.

公开(公告)号：US09756153B2

公开(公告)日：2017-09-05

申请号：US13465200

申请日：2012-05-07

Applicant: Cort Dougan ,  Victor Yodaiken

Inventor： Cort Dougan ,  Victor Yodaiken

IPC: G06F15/16 ,  H04L29/06 ,  H04L12/26 ,  H04J3/06

CPC classification number: H04L69/28 ,  H04J3/0664 ,  H04J3/0667 ,  H04L43/0858 ,  H04L43/106

Abstract: A method for improving accuracy in the computation of a one-way transfer time between two networked devices. In one aspect, variability in time transfer latency that is caused by cache loading, data structure setup time, and scheduling variability in software is reduced by initiating a first sequence of loading data structures into cache and priming scheduling, and then initiating a second sequence of calibrating the timing of a subsequent synchronization message so that the completion of the first sequence occurs just in time for the reception of the synchronization message. The method is applicable for any network time synchronization protocol, including Network Time Protocol (NTP) and Precision Time Protocol (PTP).

公开(公告)号：US09729452B2

公开(公告)日：2017-08-08

申请号：US14789235

申请日：2015-07-01

Applicant: John Earnest Averi ,  Stephen Craig Connors, Jr. ,  John Edward Dickey ,  Andrew Joshua Gottlieb

Inventor： John Earnest Averi ,  Stephen Craig Connors, Jr. ,  John Edward Dickey ,  Andrew Joshua Gottlieb

IPC: H04L12/803 ,  H04L12/701 ,  H04L12/721 ,  H04L12/729 ,  H04L12/707 ,  H04L12/725 ,  H04L12/717 ,  H04L12/863 ,  H04L12/26 ,  H04L12/833 ,  H04L12/865 ,  H04L12/927

CPC classification number: H04L47/125 ,  H04L43/062 ,  H04L43/0835 ,  H04L43/0858 ,  H04L43/087 ,  H04L43/0882 ,  H04L43/106 ,  H04L45/00 ,  H04L45/123 ,  H04L45/125 ,  H04L45/24 ,  H04L45/26 ,  H04L45/302 ,  H04L45/42 ,  H04L47/31 ,  H04L47/50 ,  H04L47/626 ,  H04L47/6275 ,  H04L47/80

Abstract: Systems and techniques are described which improve performance, reliability, and predictability of networks without having costly hardware upgrades or replacement of existing network equipment. An adaptive communication controller provides WAN performance and utilization measurements to another network node over multiple parallel communication paths across disparate asymmetric networks which vary in behavior frequently over time. An egress processor module receives communication path quality reports and tagged path packet data and generates accurate arrival times, send times, sequence numbers and unutilized byte counts for the tagged packets. A control module generates path quality reports describing performance of the multiple parallel communication paths based on the received information and generates heartbeat packets for transmission on the multiple parallel communication paths if no other tagged data has been received in a predetermined period of time to ensure performance is continually monitored. An ingress processor module transmits the generated path quality reports and heartbeat packets.

公开(公告)号：US20170222930A1

公开(公告)日：2017-08-03

申请号：US15012488

申请日：2016-02-01

Applicant: Citrix Systems, Inc.

Inventor： Praveen Raja DHANABALAN

IPC: H04L12/801 ,  H04L12/26 ,  H04L29/06

CPC classification number: H04L47/12 ,  H04L43/0858 ,  H04L43/087 ,  H04L43/0894 ,  H04L69/04 ,  H04L69/14

Abstract: An appliance for providing compression technique for jitter sensitive application through multiple network links is described. The appliance has one or more processors and includes a link quality estimator, a jitterless compressor, and a link switcher. The link quality estimator is configured to measure latency over a first link and a second link, wherein the second link has a longer latency than the first link. The jitterless compressor is configured to accumulate packets for a time period associated with a difference in latency between the second link and the first link, and determine a number of packets based on a packet size associated with the accumulated packets and bandwidth of the first link. The link switcher is configured to acquire the determined number of packets, wherein the determined number of packets have been compressed, transmit a first packet over the second link, and transmit the acquired number of packets over the first link.

公开(公告)号：US09699051B2

公开(公告)日：2017-07-04

申请号：US14685552

申请日：2015-04-13

Applicant: Ixia

Inventor： Marian Rat{hacek over (a)} ,  Codrut Dumitru R{hacek over (a)}doi ,  Vlad Stanciu ,  Bogdan Tenea

IPC: H04J1/16 ,  H04L1/00 ,  H04L12/26

CPC classification number: H04L43/0858 ,  H04L43/106

Abstract: A method for measuring one-way link delay includes transmitting a first packet from a first network device. The first packet is passively intercepted, a first copy of the first packet is transmitted to the first network device, and a second copy of the first packet is transmitted to a second network device. A time of receipt of the first copy of the first packet is recorded as an origin timestamp at the first network device. A time of receipt of the second copy of the first packet is recorded as a receive timestamp at the second network device. A second packet including the origin timestamp is transmitted from the first network device. The second packet is passively intercepted, and a first copy of the second packet is transmitted to the second network device. The first copy of the second packet is received at the second network device, and the origin timestamp is extracted from the first copy of the second packet. Link delay from the first network device to the second network device is calculated using the origin timestamp and the receive timestamp.

公开(公告)号：US20170187627A1

公开(公告)日：2017-06-29

申请号：US15456917

申请日：2017-03-13

Applicant: CISCO TECHNOLOGY, INC.

Inventor： Harsha Bharadwaj ,  Prabesh Babu Nanjundaiah

IPC: H04L12/803 ,  H04L12/801 ,  H04L12/26

CPC classification number: H04L47/122 ,  H04L43/0829 ,  H04L43/0858 ,  H04L47/11 ,  H04L47/283 ,  H04L47/32

Abstract: A method is provided in one example embodiment and includes monitoring an egress port connected to a server to detect a traffic flow comprising a plurality of data packets and determining whether one of the packets is timeout dropped at the egress port. If at least one of the packets is timeout dropped at the egress port, the method further includes detecting a destination identifier (“DID”) of the timeout dropped packet and withdrawing a device identified by the detected DID from an FC zone to which it is assigned and reactivating the zone. The method further includes determining whether the traffic flow is experiencing high wait times at the egress port and, if the traffic flow is experiencing high wait times at the egress port, detecting the DID of the traffic flow and reducing a priority of the zone to which the detected DID is assigned and reactivating the zone.

公开(公告)号：US20170185055A1

公开(公告)日：2017-06-29

申请号：US15360199

申请日：2016-11-23

Applicant: YOKOGAWA ELECTRIC CORPORATION

Inventor： Hiroaki NAKAJIMA ,  Noriko KASE ,  Kiyotaka KOZAKAI ,  Atsushi TERAYAMA

IPC: G05B13/02 ,  H04L12/26

CPC classification number: G05B13/022 ,  G05B2219/25256 ,  H04L43/0852 ,  H04L43/0858 ,  H04L43/106

Abstract: A process control system includes: a controller; at least one input and output module connected to the controller; and an allowable propagation delay value calculator in the controller, the allowable propagation delay value calculator being configured to calculate, based on the number of input and output modules connected to the controller, an allowable range for propagation delay time between the controller and the input and output module.