High modulation speed PIN-type photodiode

    公开(公告)号:US12278304B2

    公开(公告)日:2025-04-15

    申请号:US17249140

    申请日:2021-02-22

    Abstract: Various embodiments of improved PIN-type photodiodes are provided. In an example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a second absorbing layer disposed between the first absorbing layer and the n-type contact. The first absorbing layer is characterized by a first absorption coefficient and the second absorbing layer is characterized by a second absorption coefficient. The second absorption coefficient is greater than the first absorption coefficient. In another example embodiment, the PIN-type photodiode includes a p-type contact; an n-type contact; a first absorbing layer disposed between the p-type contact and the n-type contact; and a non-absorbing accelerating layer disposed between absorbing layers and non-absorbing drift layer and the n-type contact.

    PACKET LOAD-BALANCING
    603.
    发明申请

    公开(公告)号:US20250119382A1

    公开(公告)日:2025-04-10

    申请号:US18377473

    申请日:2023-10-06

    Abstract: A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes circuits to receive a packet, determine a size of the packet, determine a group of a plurality of groups of the packet based on the size of the packet, determine a port for the packet using a round-robin for the group of the packet, and send the packet via the port. Described systems include circuits to receive packet sizes from an application, initialize packet arbiter circuits based on the sizes, receive a packet associated with the application, determine a size of the packet, associate the packet with one of the packet arbiter circuits, and route the packet to a selected port.

    Frequency Control for Improved Echo Cancellation in a Full-Duplex Link

    公开(公告)号:US20250112753A1

    公开(公告)日:2025-04-03

    申请号:US18479128

    申请日:2023-10-02

    Inventor: Raanan Ivry

    Abstract: A communication device includes a transmitter, a receiver, an echo canceler, and a frequency controller. The transmitter is to transmit a transmitted (TX) signal to a peer communication device over a full-duplex link. The receiver is to receive a received (RX) signal from the peer communication device over the full-duplex link. The echo canceler is to cancel an echo component of the TX signal that is present in the RX signal. The frequency controller is to apply an adjustment to a frequency of the TX signal, the adjustment setting a phase between the TX signal and the RX signal to a value that facilitates cancellation of the echo component by the echo canceler.

    SCALABLE AND CONFIGURABLE NON-TRANSPARENT BRIDGES

    公开(公告)号:US20250110907A1

    公开(公告)日:2025-04-03

    申请号:US18477162

    申请日:2023-09-28

    Abstract: Systems and methods herein are for a Non-Transparent Bridges (NTBs) that are scalable and configurable to use equally sized or spaced windows and a common lookup database for remapping writes without completions. The equally sized or spaced windows in the address space are addressable by a starting address and a size to support communication between host machines or endpoints. The common lookup database is to allow selection of one the windows associated with a mapping between address spaces of different domains and is also to accept remapping writes through the at least one NTB to modify the mapping without need for a completion to be returned to a source of the remapping writes.

    SCALABLE AND CONFIGURABLE NON-TRANSPARENT BRIDGES

    公开(公告)号:US20250110906A1

    公开(公告)日:2025-04-03

    申请号:US18476836

    申请日:2023-09-28

    Abstract: Systems and methods herein are for a Non-Transparent Bridges (NTBs) that are scalable and configurable to use equally sized or spaced windows and a common lookup database for remapping writes without completions. The equally sized or spaced windows in the address space are addressable by a starting address and a size to support communication between host machines or endpoints. The common lookup database is to allow selection of one the windows associated with a mapping between address spaces of different domains and is also to accept remapping writes through the at least one NTB to modify the mapping without need for a completion to be returned to a source of the remapping writes.

    DISTRIBUTED DENIAL OF SERVICE (DDOS) BASED ARTIFICIAL INTELLIGENCE (AI) ACCELERATED SOLUTION USING A DATA PROCESSING UNIT (DPU)

    公开(公告)号:US20250097260A1

    公开(公告)日:2025-03-20

    申请号:US18369710

    申请日:2023-09-18

    Abstract: Apparatuses, systems, and techniques for detecting that a host device is subject to a distributed denial of service (DDOS) attack using a machine learning (ML) detection system are described. A computing system includes a data processing unit (DPU) with a network interface and a hardware acceleration engine. The DPU hosts a hardware-accelerated security service to extract features from network data and metadata from the hardware acceleration engine and sends the extracted features to the ML detection system. The ML detection system determines whether the host device is subject to a DDOS attack using the extracted features. The ML detection system can send an enforcement rule to the hardware acceleration engine responsive to a determination that the host device is subject to the DDOS attack.

    Offloaded intra-system synchronization

    公开(公告)号:US20250093905A1

    公开(公告)日:2025-03-20

    申请号:US18470452

    申请日:2023-09-20

    Abstract: In one embodiment, a peripheral device includes an oscillator, a counter to be driven by the oscillator and provide a peripheral device counter value, and processing circuitry to receive a host device counter value from a host device, read host device clock translation parameters from a host memory of the host device, the host device clock translation parameters providing translation between the host device counter value and a host device clock time, read peripheral device clock translation parameters providing a translation between the peripheral device counter value and a peripheral device clock time, read the peripheral device counter value, compute a clock correction as a function of a difference between the host device clock time and the peripheral clock time, based on the host device and peripheral device counter values and clock translation parameters, and correct the host device or peripheral device clock translation parameters based on the clock correction.

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