公开(公告)号：US20150255457A1

公开(公告)日：2015-09-10

申请号：US14196596

申请日：2014-03-04

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： NICOLAS LOUBET ,  Hong He ,  James Kuss

IPC: H01L27/088 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Methods and structures for forming finFETs of different semiconductor composition and of different conductivity type on a same wafer are described. Some finFET structures may include strained channel regions. FinFETs of a first semiconductor composition may be grown in trenches formed in a second semiconductor composition. Material of the second semiconductor composition may be removed from around some of the fins at first regions of the wafer, and may remain around fins at second regions of the wafer. A chemical component from the second semiconductor composition may be driven into the fins by diffusion at the second regions to form finFETs of a different chemical composition from those of the first regions. The converted fins at the second regions may include strain.

Abstract translation: 描述了在同一晶片上形成不同半导体组成和不同导电类型的finFET的方法和结构。 一些finFET结构可以包括应变通道区域。 可以在第二半导体组合物中形成的沟槽中生长第一半导体组合物的FinFET。 第二半导体组合物的材料可以从晶片的第一区域周围的一些鳍片周围去除，并且可以保留在晶片的第二区域周围的鳍片周围。 来自第二半导体组合物的化学成分可以通过在第二区域的扩散而被驱入散热片，以形成与第一区域不同的化学组成的finFET。 在第二区域处的转换的翅片可以包括应变。

公开(公告)号：US20150255295A1

公开(公告)日：2015-09-10

申请号：US14197790

申请日：2014-03-05

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Nicolas Loubet

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L29/045 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure.

Abstract translation: 本文中公开的一种说明性方法包括形成沟槽以形成具有初始暴露高度和侧壁的初始鳍结构，在至少初始鳍结构的侧壁上形成保护层，从而延伸沟槽的深度，从而 限定一个增加高度的翅片结构，其中绝缘材料层覆盖最终的沟槽并且将保护层置于适当位置，执行翅片氧化热退火工艺以将至少一部分高度翅片结构转换为 隔离材料，去除保护层，以及进行外延沉积工艺以在初始鳍结构的至少部分上形成半导体材料层。

公开(公告)号：US20150249153A1

公开(公告)日：2015-09-03

申请号：US14194215

申请日：2014-02-28

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/10879 ,  H01L21/2251 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/78603 ,  H01L29/78654

Abstract: Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

Abstract translation: 描述了形成基底的局部应变区域的方法和结构。 可以在衬底的局部区域的边界处形成沟槽。 局部区域的侧壁的上部可以被覆盖层覆盖，并且局部区域的侧壁的下部可能不被覆盖。 可以将转换材料形成为与局部区域的下部接触，并且加热衬底。 加热可以将化学物质从转化材料引入下部，这在局部区域中产生应力。 这些方法可以用于形成应变通道的finFET。

公开(公告)号：US09123809B2

公开(公告)日：2015-09-01

申请号：US14494979

申请日：2014-09-24

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/7849

Abstract: A transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

Abstract translation: 晶体管包括主体和构造成对身体的一部分施加应力的半导体区域。 例如，施加晶体管的沟道可以增加沟道中载流子的迁移率，从而可以降低晶体管的“导通”电阻。 例如，可以掺杂PFET的衬底，源极/漏极区域或者衬底和源/漏极区域，以对沟道进行压缩应力，从而增加沟道中空穴的迁移率。 或者，可以掺杂NFET的衬底，源极/漏极区域或衬底和源极/漏极区域两者以使通道拉伸应力，以增加沟道中电子的迁移率。

公开(公告)号：US20150243510A1

公开(公告)日：2015-08-27

申请号：US14187598

申请日：2014-02-24

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Richard S. Wise ,  Edem Wornyo ,  Yiheng Xu ,  John Zhang

IPC: H01L21/308

CPC classification number: H01L29/0661 ,  H01L21/02071 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/66621 ,  H01L29/66795 ,  H01L51/0525

Abstract: An ashing chemistry employing a combination of Cl2 and N2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.

Abstract translation: 提供采用Cl 2和N 2的组合的灰化化学品，其从图案化的金属硬掩模层的侧壁除去剩余材料，而不残留物，使得图案化的金属硬掩模层的侧壁是垂直的。 图案化的金属硬掩模层的侧壁的垂直分布可以有利地用于减少转印到下层中的图案与形成在金属硬掩模层上的图案之间的蚀刻偏压中的图案因子依赖性。 此外，灰化化学可以用于增强在金属材料层的垂直部分中的桁条的去除。

公开(公告)号：US09111801B2

公开(公告)日：2015-08-18

申请号：US13856985

申请日：2013-04-04

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/04 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L27/11

CPC classification number: H01L27/1211 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11213 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices and fabrication techniques. A semiconductor device fabrication method may include doping, in a same processing step, first and second portions of a substrate of an integrated circuit. The first portion corresponds to a doped region of a semiconductor device. The second portion corresponds to a via contact. The method may further include, after the doping, forming the gate of the semiconductor device.

Abstract translation: 集成电路器件和制造技术。 半导体器件制造方法可以包括在相同的处理步骤中掺杂集成电路的衬底的第一和第二部分。 第一部分对应于半导体器件的掺杂区域。 第二部分对应于通孔接触。 该方法还可以包括在掺杂之后形成半导体器件的栅极。

公开(公告)号：US20150228781A1

公开(公告)日：2015-08-13

申请号：US14175215

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu CAI ,  Qing LlU ,  Ruilong XIE

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material.

Abstract translation: 一种制造半导体器件的方法。 该方法可以包括在基板上形成翅片，每个翅片具有包括第一半导体材料的上翅片部分和包括电介质材料的下翅片部分。 该方法可以包括在每个下部翅片部分的侧壁中形成凹部以暴露相应的上部翅片部分的下表面，以及形成包围上翅片部分暴露的下表面的翅片的第二半导体层。 第二半导体层可以包括在第一半导体材料中产生应力的第二半导体材料。

公开(公告)号：US20150200205A1

公开(公告)日：2015-07-16

申请号：US14668482

申请日：2015-03-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： KANGGUO CHENG ,  BRUCE B. DORIS ,  ALI KHAKIFIROOZ ,  QING LIU ,  NICOLAS LOUBET ,  SCOTT LUNING

IPC: H01L27/12 ,  H01L29/10

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

Abstract translation: 一种用于半导体制造的方法包括在包括至少一个硅锗（SiGe）沟道区的衬底上提供沟道区，所述衬底包括包括第一区和第二区的多个区域。 对于第一区域中的第一n型场效应晶体管（NFET）和第一p型场效应晶体管（PFET）以及第二区域中的第二NFET和第二PFET形成栅极结构， 第一PFET形成在SiGe沟道区上。 用于第一NFET的栅极结构包括具有第一功函数的栅极材料，并且用于第一PFET，第二NFET和第二PFET的栅极结构包括具有第二功函数的栅极材料，使得提供多阈值电压器件。

公开(公告)号：US09082788B2

公开(公告)日：2015-07-14

申请号：US13906702

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Huiming Bu

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/66484 ,  H01L21/823481 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A method of making a semiconductor device includes forming an intermediate structure including second semiconductor fin portions above a first semiconductor layer, and top first semiconductor fin portions extending from respective ones of the second semiconductor fin portions. The second semiconductor fin portions are selectively etchable with respect to the top first semiconductor fin portions. A dummy gate is on the intermediate structure. The second semiconductor fin portions are selectively etched to define bottom openings under respective ones of the top first semiconductor fin portions. The bottom openings are filled with a dielectric material.

Abstract translation: 制造半导体器件的方法包括在第一半导体层之上形成包括第二半导体鳍部的中间结构以及从第二半导体鳍部中的相应半导体鳍部延伸的顶部第一半导体鳍部。 第二半导体鳍片部分相对于顶部第一半导体鳍片部分可选择性地蚀刻。 虚拟门在中间结构上。 选择性地蚀刻第二半导体鳍片部分以在顶部第一半导体鳍片部分的相应一个下限定底部开口。 底部开口填充有电介质材料。

公开(公告)号：US20150190804A1

公开(公告)日：2015-07-09

申请号：US14663981

申请日：2015-03-20

Applicant: STMicroelectronics, Inc.

Inventor： Massimiliano Pesaturo ,  Robert J. Powell

IPC: B01L3/00 ,  G01B5/00

CPC classification number: B01L3/502707 ,  B01J2219/00317 ,  B01J2219/00466 ,  B01J2219/00702 ,  B01L3/502753 ,  B01L3/502761 ,  B01L2200/0668 ,  B01L2300/16 ,  B01L2300/161 ,  C40B60/10 ,  G01B5/00 ,  Y10T428/24355

Abstract: A micro device includes a substrate and a structure configured to bind to an object or a material, or not to bind to an object or material. The structure has a roughness based on a roughness of the object or material. For example, a microarray includes a substrate and a well positioned in the substrate and configured to bind to a type of bead. The well has a roughness based on a roughness of the type of bead to which the well is configured to bind. The roughness of the well is controlled by controlling a position and number of striations in the side of the well. In another example, a moveable component of a micro device may have a roughness different from a roughness of an adjacent component, to reduce the likelihood of the moveable component sticking to the adjacent component.

Abstract translation: 微型装置包括衬底和构造成结合物体或材料的结构，或不结合物体或材料。 该结构具有基于物体或材料的粗糙度的粗糙度。 例如，微阵列包括基底和定位在基底中并且被配置为结合一种珠粒的孔。 井具有基于井的类型的粗糙度的孔的粗糙度，孔被构造成结合。 井的粗糙度通过控制井的位置和条纹的数量来控制。 在另一示例中，微型装置的可移动部件可以具有与相邻部件的粗糙度不同的粗糙度，以减少可移动部件粘附到相邻部件的可能性。