公开(公告)号：US20160099326A1

公开(公告)日：2016-04-07

申请号：US14965519

申请日：2015-12-10

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Sébastien BARNOLA ,  Yves MORAND ,  Heimanu NIEBOJEWSKI

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/49 ,  H01L29/45 ,  H01L29/06

CPC classification number: H01L29/42372 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

公开(公告)号：US20160087092A1

公开(公告)日：2016-03-24

申请号：US14959430

申请日：2015-12-04

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Yves Morand ,  Romain Wacquez ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7856

Abstract: A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide.

Abstract translation: 翅片MOS晶体管由SOI型结构制成，其包括在涂覆半导体支撑体的氧化硅层上的半导体层。 从半导体层的表面形成的沟槽限定半导体层中的至少一个鳍，该沟槽至少延伸到半导体支撑件的上表面。 在位于翅片下方的氧化硅层的一部分侧面上的蚀刻凹槽填充有可在氧化硅上蚀刻的材料。

公开(公告)号：US20160049189A1

公开(公告)日：2016-02-18

申请号：US14813278

申请日：2015-07-30

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Christophe Lecocq ,  Kaya Can Akyel ,  Amit Chhabra ,  Dibya Dipti

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L27/1104

Abstract: An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.

Abstract translation: SRAM单元由FDSOI型NMOS和PMOS晶体管形成。 掺杂阱在NMOS和PMOS晶体管的下方延伸，并通过绝缘层与其分离。 偏置电压施加到掺杂阱。 施加的偏置电压根据存储单元的状态进行调整。 例如，感测存储器单元的温度，并根据检测到的温度调整偏置电压。 偏置电压的调整被配置为使得NMOS和PMOS晶体管的阈值电压分别基本上等于n和p个目标阈值电压。

公开(公告)号：US09257956B2

公开(公告)日：2016-02-09

申请号：US14030357

申请日：2013-09-18

Applicant: STMicroelectronics SA

Inventor： Jean-Christophe Ricard ,  Cedric Durand ,  Frederic Gianesello

IPC: H03H7/01 ,  H03H3/00 ,  H03H7/12 ,  H03H7/075 ,  H03H7/46

CPC classification number: H03H7/0138 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/0161 ,  H03H7/075 ,  H03H7/12 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/1783 ,  H03H7/1791 ,  H03H7/463

Abstract: A passive filter may include at least one elliptical filter unit and at least one asymmetric rejection filter unit coupled in series with the elliptical filter unit. The at least one asymmetric rejection filter unit may have a frequency response curve that includes a dip with different attenuations on either side, and an overshoot upon exiting the dip at the side with the lower attenuation.

Abstract translation: 无源滤波器可以包括至少一个椭圆滤波器单元和与椭圆滤波器单元串联耦合的至少一个不对称拒绝滤波器单元。 所述至少一个不对称拒绝滤波器单元可以具有频率响应曲线，其包括在任一侧具有不同衰减的倾角，以及在具有较低衰减的一侧退出倾斜时的过冲。

公开(公告)号：US09246006B2

公开(公告)日：2016-01-26

申请号：US14453800

申请日：2014-08-07

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA

Inventor： Perrine Batude ,  Frederic Mazen ,  Benoit Sklenard ,  Shay Reboh

IPC: H01L21/00 ,  H01L29/786 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/78603 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/1045 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78654

Abstract: A method for manufacturing a transistor is provided, including amorphization and doping, by one or more localized implantations, of given regions of source and drain blocks based on crystalline semi-conductor material disposed on an insulating layer of a semi-conductor on insulator substrate, the implantations being carried out so as to conserve at a surface of said blocks zones of crystalline semi-conductor material on regions of amorphous semi-conductor material; and recrystallization of at least one portion of said given regions.

Abstract translation: 根据设置在绝缘体上半导体衬底的绝缘层上的晶体半导体材料，通过一个或多个局部注入，提供源极和漏极区域的给定区域的非晶化和掺杂的晶体管的制造方法， 进行注入以便在非晶半导体材料的区域上在晶体半导体材料的所述块区的表面上保存; 以及所述给定区域的至少一部分的重结晶。

公开(公告)号：US09239506B2

公开(公告)日：2016-01-19

申请号：US14271723

申请日：2014-05-07

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert Manouvrier

IPC: G02F1/035 ,  G02F1/225 ,  G02F1/015 ,  G02F1/025 ,  H01L33/00 ,  G02F1/21

CPC classification number: G02F1/2257 ,  G02F1/015 ,  G02F1/025 ,  G02F2001/212 ,  G02F2203/20 ,  H01L33/0012

Abstract: A semiconductor electro-optical phase shifter comprises a central zone (I1, I2) having a minimum doping level; first and second lateral zones (N+, P+) flanking the central zone along a first axis, respectively N and P-doped, so as to form a P-I-N junction between the first and second lateral zones. The central zone comprises first and second optical action zones (I1, I2) separated along the first axis. The second lateral zone is doped discontinuously along a second axis perpendicular to the first axis. Two electrical control terminals (A, C) are provided, one in contact with the first lateral zone, and the other in contact with doped portions of the second lateral zone.

Abstract translation: 半导体电光移相器包括具有最小掺杂水平的中心区（I1，I2）; 第一和第二侧向区域（N +，P +）分别沿着第一轴线分别位于中心区域N和P掺杂，以便在第一和第二侧向区域之间形成P-I-N结。 中心区域包括沿着第一轴线分离的第一和第二光学作用区域（I1，I2）。 第二横向区域沿着垂直于第一轴线的第二轴线不连续地掺杂。 设置两个电气控制端子（A，C），一个与第一侧向区域接触，另一个与第二侧向区域的掺杂部分接触。

公开(公告)号：US09214485B2

公开(公告)日：2015-12-15

申请号：US14452702

申请日：2014-08-06

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Laurent Frey ,  Michel Marty

IPC: H01L27/146 ,  G02B5/28

CPC classification number: H01L27/14621 ,  G02B5/28 ,  G02B5/288 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14649 ,  H01L27/14685

Abstract: A multilayer optical filter is provided for an integrated circuit including a substrate and a metallization layer interconnection part. The optical filter is formed from a first filter part located within the interconnection part and positioned over a photosensitive region of the substrate. The optical filter further includes a second filter part positioned above the first filter part and the interconnection part. The first and second filter parts each include a metal layer. The first and second filter parts are separated from each other as a function of a wavelength in vacuum of an optical signal to be filtered and received by the photosensitive region.

Abstract translation: 为包括基板和金属化层互连部件的集成电路提供了多层光学滤波器。 滤光器由位于互连部分内的第一过滤器部分形成，并位于衬底的光敏区域上。 光滤波器还包括位于第一滤波器部分和互连部分上方的第二滤波器部分。 第一和第二过滤器部件各自包括金属层。 第一和第二滤光器部分根据要被滤光并由感光区域接收的光信号的真空中的波长彼此分离。

公开(公告)号：US09209211B2

公开(公告)日：2015-12-08

申请号：US14660847

申请日：2015-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Robert Manouvrier ,  Pascal Fonteneau ,  Xavier Montagner

IPC: H01L27/146 ,  H01L29/423

CPC classification number: H01L27/14614 ,  H01L27/14607 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L29/4236

Abstract: The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region.

Abstract translation: 本发明涉及一种光电二极管，包括：P导电型衬底区域，用于收集当衬底区域的后表面接收光时出现的电荷的电荷收集区域，所述收集区域包括形成深的N导电类型区域 在基板区域中，形成在基板区域中的N导电型读取区域和隔离的转移栅极，形成在与N导电型区域的侧面相反延伸的深隔离沟槽中的基板区域中， 并且被布置为接收栅极电压以将存储在收集区域中的电荷转移到读取区域。

公开(公告)号：US20150311277A1

公开(公告)日：2015-10-29

申请号：US14640705

申请日：2015-03-06

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Vincent Fiori ,  Sebastien Gallois-Garreignot ,  Denis Rideau ,  Clement Tavernier

IPC: H01L29/04 ,  H01L29/10

CPC classification number: H01L29/045 ,  H01L23/522 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A substrate includes an active region oriented along a crystallographic face (100) and limited by an insulating region. A MOS transistor includes a channel oriented longitudinally along a crystallographic direction of the type. A basic pattern made of metal and formed in the shape of a T is electrically inactive and situated over an area of the insulating region adjacent a transverse end of the channel. A horizontal branch of the T-shaped basic pattern is oriented substantially parallel to the longitudinal direction of the channel.

Abstract translation: 衬底包括沿结晶面（100）取向并被绝缘区域限制的有源区。 MOS晶体管包括沿着<110>型晶体方向纵向取向的通道。 由金属形成并形成为T形状的基本图案是电惰性的，并且位于与通道的横向端部相邻的绝缘区域的区域上。 T形基本图案的水平分支基本上平行于通道的纵向定向。

公开(公告)号：US20150287722A1

公开(公告)日：2015-10-08

申请号：US14435004

申请日：2013-10-11

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  STMicroelectronics SA

Inventor： Bastien Giraud ,  Philippe Flatresse ,  Jean-Philippe Noel ,  Bertrand Pelloux-Prayer

IPC: H01L27/092 ,  H01L27/12

CPC classification number: H01L27/092 ,  H01L21/823892 ,  H01L27/1203

Abstract: An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.

Abstract translation: 集成电路包括具有第一和第二单元的衬底，第一和第二单元具有第一和第二FDSOI场效应晶体管。 在地平面下方有第一和第二接地层，一个埋置的氧化物层和一个和第二个井。 第一阱和第一接地层具有相同的掺杂，第二阱和第二接地层具有相同的掺杂。 第一和第二单元相邻并且它们的晶体管沿第一方向排列。 第一单元的阱和第二单元的第一阱与第二阱相反地掺杂。 控制装置利用第一掺杂将第一电偏压施加到阱，并且通过第二掺杂向阱施加第二电偏压。 第一单元和第二单元的晶体管具有不同的阈值电压电平。