公开(公告)号：US20240243087A1

公开(公告)日：2024-07-18

申请号：US18620569

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Ryan Joseph Carrazzone ,  Anastasia Arrington ,  Haobo Chen ,  Hongxia Feng ,  Catherine Ka-Yan Mau ,  Kyle Matthew McElhinny ,  Dingying Xu

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/1146 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/1357 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2924/384

Abstract: Systems, apparatus, articles of manufacture, and methods to reduce variation in height of bumps after flow are disclosed. An example apparatus includes a substrate of an integrated circuit package, a first bump on the substrate, a second bump on the substrate, and a third bump on the substrate. The first bump includes first solder on a first metal pad. The first metal pad has a first width and a first thickness. The second bump includes second solder on a second metal pad. The second metal pad has a second width and a second thickness. The second width is less than the first width. The second thickness matches the first thickness. The third bump includes third solder on a third metal pad. The third metal pad has a third width. The third width less than the second width.

公开(公告)号：US20240242217A1

公开(公告)日：2024-07-18

申请号：US18618610

申请日：2024-03-27

Applicant: Intel Corporation

Inventor： Vaibhavdeep Singh ,  Hemant Sathish ,  Rohit Sundaram ,  Anjali Praveen

IPC: G06Q20/40

CPC classification number: G06Q20/4014

Abstract: Methods and apparatus for one-time password detection and alert are disclosed. A disclosed example apparatus includes machine readable instructions, and at least one processor circuit to be programmed by the machine readable instructions to classify, with a trained machine-learning model, messages of a messaging platform of a computing device as one of a financial transaction or a non-financial transaction, and provide a warning based on a one-time password (OTP) message of the messages being classified as a financial transaction.

公开(公告)号：US20240242128A1

公开(公告)日：2024-07-18

申请号：US18621771

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Ria Cheruvu ,  Anahit Tarkhanyan

IPC: G06N20/00 ,  G06F9/30 ,  H04L9/32

CPC classification number: G06N20/00 ,  G06F9/30101 ,  H04L9/3242 ,  H04L9/3247

Abstract: Embodiments are directed to immutable watermarking for authenticating and verifying artificial intelligence (AI)-generated output. An embodiment of a system includes a processor of a monitoring system, wherein the processor is to: receive first content from a first device and second content from a second device, wherein the first content comprises output of inferences of a machine learning (ML) model as applied to captured content at the first device; extracting, from a digital signature corresponding to the first content, a global unique identifier (GUID) of the ML model that generated the first content; verify the extracted GUID against data obtained from a shared registry, the data comprising identifying information of the ML model including the GUID; in response to successfully verifying the extracted GUID, provide the first content for consumption at an application and indicate that the content is generated by the ML model having verified authenticity.

公开(公告)号：US20240241805A1

公开(公告)日：2024-07-18

申请号：US18560270

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Tao Xu ,  Shijie Liu ,  Kevin Yufu Li ,  Lei Zhu ,  Sarathy Jayakumar

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G06F2201/85

Abstract: A disclosed example includes setting a corrected error threshold value for a memory rank; recording, in a corrected error bank record memory structure, corrected errors for memory banks in the memory rank; maintaining, in the corrected error bank record memory structure, counts of the corrected errors for the memory banks; and notifying runtime error handling circuitry in response to at least one of the counts of the corrected errors satisfying a threshold value.

公开(公告)号：US20240241446A1

公开(公告)日：2024-07-18

申请号：US18620262

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Marvin Paik ,  Charles H. Wallace ,  Leonard Guler ,  Elliot N. Tan ,  Shengsi Liu ,  Vivek Vishwakarma ,  Izabela Samek ,  Mohammadreza Soleymaniha

IPC: G03F7/20 ,  G03F7/00 ,  H01L21/027

CPC classification number: G03F7/2022 ,  G03F7/2004 ,  G03F7/201 ,  G03F7/70033 ,  G03F7/7005 ,  G03F7/70525 ,  G03F7/7055 ,  G03F7/70725 ,  H01L21/0275

Abstract: Apparatus and methods are disclosed. An example lithography apparatus includes an ultraviolet (UV) source to expose a photoresist layer to UV light; and an extreme ultraviolet (EUV) source coupled to the UV source, the EUV source to expose the photoresist layer to EUV light to via a photomask, a combination of the UV light and the EUV light provide a pattern on the photoresist layer when a developer solution is applied to the photoresist layer.

公开(公告)号：US20240241434A1

公开(公告)日：2024-07-18

申请号：US18620107

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Yongbae Kim

IPC: G03F1/60 ,  G03F1/54

CPC classification number: G03F1/60 ,  G03F1/54

Abstract: Photomasks having intermediate barrier layers are disclosed. An example photomask comprises a substrate including a multilayer region, the multilayer region including alternating layers of a first material and a second material different from the first material, a capping layer, and an intermediate layer separating the capping layer and the substrate, the intermediate layer including a third material different from the first material and different from the second material.

公开(公告)号：US12041315B2

公开(公告)日：2024-07-16

申请号：US17129957

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Zhaohua Yi ,  Laurent Cariou ,  Dave Cavalcanti

IPC: H04N21/61 ,  H04N21/4363 ,  H04N21/6375

CPC classification number: H04N21/615 ,  H04N21/43637 ,  H04N21/6375

Abstract: Provided herein are apparatus and methods for improving transmission efficiency of video content for Wireless Fidelity (Wi-Fi). An apparatus for a Wi-Fi device comprises a Radio Frequency (RF) interface and processing circuitry coupled with the RF interface. The processing circuitry is to encode a Medium Access Control (MAC) frame, to carry video content to be transmitted to one or more other Wi-Fi devices connected with the Wi-Fi device; encapsulate the MAC frame into a physical (PHY) frame, the PHY frame is to include an additional byte in a high-efficiency signal-A (HE-SIG-A) field, to indicate whether the MAC frame is encoded as an original MAC frame including one Frame Check Sequence (FCS) or a video content specific MAC frame including more than one FCSs; and transmit the PHY frame, via the RF interface, to the one or more other Wi-Fi devices.

公开(公告)号：US12041250B2

公开(公告)日：2024-07-16

申请号：US16739584

申请日：2020-01-10

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Basel Salahieh

IPC: H04N19/82 ,  H04N19/132 ,  H04N19/40 ,  H04N21/2365 ,  H04N21/4402

CPC classification number: H04N19/40 ,  H04N19/132 ,  H04N21/2365 ,  H04N21/4402

Abstract: An example apparatus for transcoding multi-dimensional video includes a multi-dimensional video decoder to decode a first bitstream of multi-dimensional video. The apparatus also includes a transcoder to transcode the decoded first bitstream to generate transcoded multi-dimensional data. The apparatus also further includes a multi-dimensional video encoder to generate a second bitstream based on the transcoded multi-dimensional data.

公开(公告)号：US12040286B2

公开(公告)日：2024-07-16

申请号：US17886380

申请日：2022-08-11

Applicant: Intel Corporation

Inventor： Eunyong Chung ,  Moon Young Jang

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/56 ,  H01L21/67 ,  H01L23/31 ,  H01L25/065 ,  H05K1/18

CPC classification number: H01L23/562 ,  H01L21/02362 ,  H01L21/565 ,  H01L21/67288 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0655 ,  H05K1/181 ,  H01L2224/02379 ,  H01L2924/3511

Abstract: Fan-out panel level packages (FOPLPs) comprising warpage control structures and techniques of formation are described. An FOPLP may comprise one or more redistribution layers; a semiconductor die on the one or more redistribution layers; one or more warpage control structures adjacently located next to the semiconductor die; and a mold compound encapsulating the semiconductor die and the one or more warpage control structures on the one or more redistribution layers. The FOPLP can be coupled a board (e.g., a printed circuit board, etc.). The warpage control structures can assist with minimizing or eliminating unwanted warpage, which can occur during or after formation of an FOPLP or a packaged system. In this way, the warpage control structures can assist with reducing costs associated with semiconductor packaging and/or manufacturing of an FOPLP or a packaged system.

公开(公告)号：US12040276B2

公开(公告)日：2024-07-16

申请号：US17888177

申请日：2022-08-15

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Wei-Lun Kane Jen ,  Jonathan L. Rosch ,  Islam A. Salama ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/16227

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.