中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

855 records (took 0.034 seconds)

    Variable Delay Element
    641.
    发明申请
    Variable Delay Element 有权
    可变延迟元件

    公开(公告)号：US20150028930A1

    公开(公告)日：2015-01-29

    申请号：US14337896

    申请日：2014-07-22

    Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

    Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

    IPC: H03H11/26

    CPC classification number: H03K5/134 ,  H03K5/13 ,  H03K2005/00032 ,  H03K2005/00208 ,  H03K2005/00215 ,  H03K2217/0018

    Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages , to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.

    Abstract translation: 延迟电路包括第一和第二晶体管和偏置电路。 第一晶体管具有耦合到延迟电路的输入节点的控制节点，耦合到第一电源电压的第一主电流节点和耦合到延迟电路的输出节点的第二主电流节点。 第二晶体管具有耦合到输入节点的控制节点，耦合到第二电源电压的第一主电流节点和耦合到输出节点的第二主电流节点。 偏置电路被配置为产生第一和第二差分控制电压，以将第一差分控制电压施加到第一晶体管的另一控制节点，并将第二差分控制电压施加到第二晶体管的另一个控制节点。

    ELECTRO-OPTICAL PHASE SHIFTER HAVING A LOW ABSORPTION COEFFICIENT
    642.
    发明申请
    ELECTRO-OPTICAL PHASE SHIFTER HAVING A LOW ABSORPTION COEFFICIENT 有权
    具有低吸收系数的电光相变器

    公开(公告)号：US20140376852A1

    公开(公告)日：2014-12-25

    申请号：US14263068

    申请日：2014-04-28

    Applicant: STMICROELECTRONICS SA

    Inventor： Jean-Robert MANOUVRIER

    IPC: G02F1/025

    CPC classification number: G02F1/025

    Abstract: A semiconductor electro-optical phase shifter may include a central zone configured to be placed in an optical waveguide and doped at a first conductivity type, a first lateral zone adjacent a first face of the central region and doped at a second conductivity type, and a second lateral zone adjacent a second face of the central zone and doped at the second conductivity type.

    Abstract translation: 半导体电光移相器可以包括被配置为放置在光波导中并以第一导电类型掺杂的中心区，邻近中心区的第一面并以第二导电类型掺杂的第一横向区， 第二横向区域，邻近中心区域的第二面并以第二导电类型掺杂。

    CIRCUIT AND METHOD FOR SIGNAL CONVERSION
    645.
    发明申请
    CIRCUIT AND METHOD FOR SIGNAL CONVERSION 有权
    电路与信号转换方法

    公开(公告)号：US20140361915A1

    公开(公告)日：2014-12-11

    申请号：US14294300

    申请日：2014-06-03

    Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

    Inventor： Stéphane LE TUAL ,  Pratap Narayan SINGH

    IPC: H03M1/08 ,  H03K3/013

    CPC classification number: H03M1/08 ,  G11C27/024 ,  G11C27/026 ,  H03K3/013 ,  H03K19/018528

    Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CPGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).

    Abstract translation: 本发明涉及一种电路，包括：具有耦合到第一电压信号（CNVDD）的第一主电流节点的第一晶体管（202），耦合到第二电压信号（CPVDD）的控制节点和耦合到第一电流信号 输出节点（206）; 第二晶体管（204），其具有耦合到第三电压信号（CPGND）的第一主电流节点，耦合到第四电压信号（CPGND）的控制节点和耦合到所述电路的所述输出节点的第二主电流节点; 以及适于基于一对差分输入信号（CP，CN）产生所述第一，第二，第三和第四电压信号的电路（210,212），其中所述第一和第二电压信号都参考第一电源电压 VDD），并且其中所述第三和第四电压信号都参考第二电源电压（GND）。

    OPTICAL MODULATOR WITH AUTOMATIC BIAS CORRECTION
    646.
    发明申请
    OPTICAL MODULATOR WITH AUTOMATIC BIAS CORRECTION 有权
    具有自动偏差校正的光学调制器

    公开(公告)号：US20140241657A1

    公开(公告)日：2014-08-28

    申请号：US14182033

    申请日：2014-02-17

    Applicant: STMICROELECTRONICS SA

    Inventor： Jean-Robert MANOUVRIER

    IPC: G02F1/01 ,  G01J9/00 ,  G01J9/02 ,  G02F1/025

    CPC classification number: G02F1/0123 ,  G01J9/00 ,  G01J9/02 ,  G02F1/025 ,  G02F1/218 ,  G02F1/2257 ,  G02F2001/212 ,  G02F2201/58 ,  G02F2203/50 ,  H04B10/5053 ,  H04B10/50575

    Abstract: An optical modulator uses an optoelectronic phase comparator configured to provide, in the form of an electrical signal, a measure of a phase difference between two optical waves. The phase comparator includes an optical directional coupler having two coupled channels respectively defining two optical inputs for receiving the two optical waves to be compared. Two photodiodes are configured to respectively receive the optical output powers of the two channels of the directional coupler. An electrical circuit is configured to supply, as a measure of the optical phase shift, an electrical signal proportional to the difference between the electrical signals produced by the two photodiodes.

    Abstract translation: 光调制器使用光电相位比较器，其被配置为以电信号的形式提供两个光波之间的相位差的量度。 相位比较器包括具有两个耦合通道的光学定向耦合器，该耦合通道分别限定用于接收要比较的两个光波的两个光学输入。 两个光电二极管被配置为分别接收定向耦合器的两个通道的光输出功率。 电路被配置为提供与两个光电二极管产生的电信号之间的差成比例的电信号作为光相移的测量。

    ANTENNA CIRCUIT USING MULTIPLE INDEPENDENT ANTENNAS SIMULTANEOUSLY THROUGH A SINGLE FEED
    648.
    发明申请
    ANTENNA CIRCUIT USING MULTIPLE INDEPENDENT ANTENNAS SIMULTANEOUSLY THROUGH A SINGLE FEED 有权
    通过单次进给同时使用多个独立天线的天线电路

    公开(公告)号：US20140145897A1

    公开(公告)日：2014-05-29

    申请号：US14058515

    申请日：2013-10-21

    Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

    Inventor： Florence SONNERAT ,  Romain PILARD ,  Frédéric GIANESELLO ,  Cédric DURAND

    IPC: H01Q21/30 ,  H01Q21/00

    CPC classification number: H01Q21/30 ,  H01Q1/243 ,  H01Q5/371 ,  H01Q9/42 ,  H01Q21/0087 ,  H01Q21/28 ,  H04B1/0057 ,  Y10T29/49018

    Abstract: An antenna circuit includes a first antenna tuned to a first fundamental frequency and a second antenna tuned to a second fundamental frequency different from the first fundamental frequency. A first filter has a first terminal connected to the first antenna and attenuates the frequency components outside of a band defined by the first fundamental frequency or its harmonics. A second filter has a first terminal coupled to the second antenna and attenuates the frequency components outside of a band defined by the second fundamental frequency or its harmonics. A passive recombination element couples the second terminals of the two filters to a common terminal.

    Abstract translation: 天线电路包括调谐到第一基频的第一天线和被调谐到与第一基频不同的第二基频的第二天线。 第一滤波器具有连接到第一天线的第一端子，并且衰减由第一基频或其谐波限定的频带之外的频率分量。 第二滤波器具有耦合到第二天线的第一端子，并且衰减由第二基频或其谐波限定的频带之外的频率分量。 被动复合元件将两个滤波器的第二端子耦合到公共端子。

    ADAPTIVE MULTI-STAGE SLACK BORROWING FOR HIGH PERFORMANCE ERROR RESILIENT COMPUTING
    649.
    发明申请
    ADAPTIVE MULTI-STAGE SLACK BORROWING FOR HIGH PERFORMANCE ERROR RESILIENT COMPUTING 有权
    适用于高性能误差计算的自适应多级滑块

    公开(公告)号：US20140035644A1

    公开(公告)日：2014-02-06

    申请号：US14045642

    申请日：2013-10-03

    Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

    Inventor： Chittoor PARTHASARATHY ,  Nitin CHAWLA ,  Kallol CHATTERJEE ,  Pascal URARD

    IPC: H03K3/02

    CPC classification number: H03K3/02 ,  H03K3/0375

    Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

    Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 该应用提出了一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。

    ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges
    650.
    发明申请
    ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges 有权
    ON-SOI集成电路包括用于防止静电放电的晶闸管（SCR）

    公开(公告)号：US20140015052A1

    公开(公告)日：2014-01-16

    申请号：US13932371

    申请日：2013-07-01

    Applicant: STMicroelectronics SA ,  Commissariat a l'energie atomique et aux energies alternatives

    Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

    IPC: H01L27/12

    CPC classification number: H01L27/1203 ,  H01L27/0262 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207

    Abstract: An integrated circuit includes an UTBOX insulating layer under and plumb with first and second electronic components, and corresponding ground planes and oppositely-doped wells made plumb with them. The wells contact with corresponding ground planes. A pair of oppositely doped bias electrodes, suitable for connecting corresponding bias voltages, contacts respective wells and ground planes. A third electrode contacts the first well. A first trench isolates one bias electrode from the third electrode and extends through the layer and into the first well. A second trench isolates the first bias electrode from one component. This trench has an extent that falls short of reaching an interface between the first ground plane and the first well.

    Abstract translation: 集成电路包括在第一和第二电子部件下面并且铅垂的UTBOX绝缘层，以及相应的接地平面和与其相反的相对掺杂的阱。 油井与相应的地面接触。 一对相对掺杂的偏置电极适于连接相应的偏置电压，接触相应的阱和接地层。 第三电极接触第一阱。 第一沟槽将一个偏置电极与第三电极隔离并延伸穿过该层并进入第一阱。 第二沟槽将第一偏置电极与一个部件隔离。 该沟槽的程度不足以达到第一接地层与第一井之间的界面。

Patent Agency Ranking