公开(公告)号：US10134894B2

公开(公告)日：2018-11-20

申请号：US14985264

申请日：2015-12-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anand Kumar ,  Ankit Agrawal

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/311 ,  H01L21/762 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/786

Abstract: Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.

公开(公告)号：US10128913B2

公开(公告)日：2018-11-13

申请号：US15669380

申请日：2017-08-04

Applicant: STMicroelectronics International N.V.

Inventor： Vinko Kunc ,  Maksimiljan Stiglic ,  Kosta Kovacic ,  Albin Pevec ,  Anton Stern

IPC: H04Q5/22 ,  H04B5/00 ,  G06K19/07 ,  G06K7/10

Abstract: A circuit of an actively transmitting tag includes an antenna, a digitizer, a voltage-controlled oscillator (VCO), an output amplifier, a phase-displacement detector, and a regulator. The input of the digitizer connects to the antenna. The outputs of the digitizer and the output amplifier are connected to the input terminals of the phase-displacement detector. The output amplifier connects the output of the VCO to the antenna and the regulator connects the output of the phase-displacement detector to the VCO.

公开(公告)号：US10097799B2

公开(公告)日：2018-10-09

申请号：US15958244

申请日：2018-04-20

Applicant: STMicroelectronics International N.V.

Inventor： Mahesh Chandra ,  Brejesh Lall

IPC: H04N9/45 ,  H04N5/347 ,  H04N9/04

Abstract: An image sensor device may include an array of image sensing pixels with adjacent image sensing pixels being arranged in macropixel, and a processor coupled to the array of image sensing pixels. The processor may be configured to receive pixel signals from the array of image sensing pixels, and arrange the received pixel signals into macropixel signal sets for respective macropixels. The processor may be configured to perform, in parallel, an image enhancement operation on the received pixel signals for each macropixel signal set to generate enhanced macropixel signals, and transmit the enhanced macropixel signals.

公开(公告)号：US20180287617A1

公开(公告)日：2018-10-04

申请号：US15475274

申请日：2017-03-31

Applicant: STMicroelectronics International N.V.

Inventor： Anand Kumar ,  Nitin Gupta ,  Nitin Jain

IPC: H03L1/00 ,  H03L7/099 ,  H03L7/183

Abstract: An electronic device disclosed herein includes a locked loop circuit configured to receive a reference signal intended to have an intended frequency, wherein the locked look circuit is intended to generate an intended output signal having an intended frequency equal to the intended frequency multiplied by an intended multiplier. A frequency counter counts a number of pulses of the reference signal during a time window so as to determine an actual frequency of the reference signal. A control circuit determines an actual multiplier for the locked loop circuit that, when multiplied by the actual frequency of the reference signal, causes the locked loop circuit to generate an actual output signal having an actual frequency equal to the intended frequency.

公开(公告)号：US10050524B1

公开(公告)日：2018-08-14

申请号：US15800896

申请日：2017-11-01

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/18 ,  H02M3/07 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02

Abstract: A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.

公开(公告)号：US10049237B2

公开(公告)日：2018-08-14

申请号：US15473074

申请日：2017-03-29

Applicant: STMicroelectronics International N.V

Inventor： Kosta Kovacic ,  Albin Pevec ,  Maksimiljan Stiglic

IPC: G06K7/10 ,  G06K19/07

Abstract: Embodiments provide a method for sending a message from an RFID transponder to a reader during a transmission frame using active load modulation, the method comprising. An encoded bit signal has a first logic level during first time segments within the transmission frame and a second logic level during second time segments within the transmission frame. The first time segments include an initial time segment of the transmission frame. A transmission signal is generated based on the encoded bit signal. The transmission signal is generated having a first phase depending on the first logic level during the first time segments, a second phase depending on the second logic level during the second time segments, and the second phase during a time interval preceding the transmission frame.

公开(公告)号：US10037794B1

公开(公告)日：2018-07-31

申请号：US15660371

申请日：2017-07-26

Applicant: STMicroelectronics International N.V.

Inventor： Dhori Kedar Janardan ,  Abhishek Pathak ,  Shishir Kumar

IPC: G11C5/06 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C7/227 ,  G11C11/419 ,  G11C2207/002

Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

公开(公告)号：US10024888B2

公开(公告)日：2018-07-17

申请号：US15618269

申请日：2017-06-09

Applicant: STMicroelectronics International N.V.

Inventor： Daljeet Kumar ,  Tapas Nandy ,  Surendra Kumar

IPC: G01R19/04 ,  G01R19/25

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

公开(公告)号：US10008258B2

公开(公告)日：2018-06-26

申请号：US15296567

申请日：2016-10-18

Applicant: STMicroelectronics International N.V

Inventor： Piyush Jain ,  Vivek Asthana ,  Naveen Batra

IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/12

Abstract: A circuit can be used, for example, with a multi-supply memory device. The circuit includes a first conductor and a second conductor. A first transistor has a current path coupled between the first conductor and the second conductor. A second transistor also has a current path coupled between the first conductor and the second conductor. A pulse generator circuit has an input coupled to a control terminal of the first transistor and an output coupled to a control terminal of the second transistor.

公开(公告)号：US20180166128A1

公开(公告)日：2018-06-14

申请号：US15375987

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Abhishek Pathak

IPC: G11C11/419 ,  G11C11/418 ,  G06F1/06 ,  G06F13/16

CPC classification number: G11C11/419 ,  G06F1/06 ,  G06F13/1689 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.