公开(公告)号：US20140104935A1

公开(公告)日：2014-04-17

申请号：US14023970

申请日：2013-09-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G11C7/10 ,  G11C11/419 ,  G11C8/18

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/02 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract translation: 半导体存储器系统包括第一半导体存储器管芯和第二半导体存储器管芯。 第一半导体存储器管芯包括主数据接口，用于在写操作期间接收输入数据流，并将输入数据流反序列化为第一多个数据流，并且还包括耦合到主数据接口的辅数据接口， 发送第一多个数据流。 第二半导体存储器管芯包括耦合到第一半导体存储器管芯的次级数据接口的次级数据接口，以接收第一多个数据流。

公开(公告)号：US20140032830A1

公开(公告)日：2014-01-30

申请号：US13949982

申请日：2013-07-24

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard S. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: G11C11/406 ,  G11C21/00

CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration.

Abstract translation: 存储器组件包括包含动态随机存取存储器（DRAM）存储单元的存储器核心和用于接收外部命令的第一电路。 外部命令包括指定发送从存储器核心访问的数据的读取命令。 存储器组件还包括响应于读取命令和在校准期间可操作以提供至少第一数据模式和第二数据模式的读取命令和模式寄存器电路将数据发送到外部总线的第二电路。 在校准期间，第一数据模式和第二数据模式中的所选择的一个被响应于在校准期间接收到的读命令，被第二电路发送到外部总线上。

公开(公告)号：US08553475B2

公开(公告)日：2013-10-08

申请号：US13670343

申请日：2012-11-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/22

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/40615 ,  G11C11/409 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

公开(公告)号：US20130250706A1

公开(公告)日：2013-09-26

申请号：US13899844

申请日：2013-05-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C8/18

CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

Abstract: A memory module having memory components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective memory components, and the address/control signal path and clock signal path are coupled in common to all the memory components. The address/control signal path extends along the memory components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective memory components at progressively later times corresponding to relative positions of the memory components.

Abstract translation: 具有存储器组件，终端结构，地址/控制信号路径，时钟信号路径，多个数据信号路径和多个选通信号路径的存储器模块。 选通信号路径和数据信号路径被耦合到相应的存储器组件，并且地址/控制信号路径和时钟信号路径共同耦合到所有存储器组件。 地址/控制信号路径沿着存储器组件延伸到终端结构，使得朝着终端结构传播的控制信号在对应于存储器组件的相对位置的逐渐更新的时间到达各个存储器组件的地址/控制输入。

公开(公告)号：US12298920B2

公开(公告)日：2025-05-13

申请号：US18590200

申请日：2024-02-28

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Frederick A. Ware

IPC: G06F12/14 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

公开(公告)号：US20250087261A1

公开(公告)日：2025-03-13

申请号：US18904454

申请日：2024-10-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G06F12/06 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US12235712B2

公开(公告)日：2025-02-25

申请号：US18535953

申请日：2023-12-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/16

Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

公开(公告)号：US20250061062A1

公开(公告)日：2025-02-20

申请号：US18806549

申请日：2024-08-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F12/0895 ,  G06F12/0802 ,  G06F12/0846 ,  G06F12/1027 ,  G11C8/06

Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

公开(公告)号：US12228961B2

公开(公告)日：2025-02-18

申请号：US18629138

申请日：2024-04-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F1/12 ,  G06F1/04 ,  G06F1/08 ,  G11C7/02 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G06F1/06 ,  G06F1/10

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

公开(公告)号：US12213548B2

公开(公告)日：2025-02-04

申请号：US17852266

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G06F12/02 ,  A41D3/04 ,  A45F3/04 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0895 ,  G11C5/04 ,  G11C11/00 ,  G11C14/00 ,  A45F3/00 ,  G11C7/22 ,  G11C11/4076

Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive non-volatile memory. Local controller manages communication between the DRAM cache and non-volatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.