公开(公告)号：US20160034399A1

公开(公告)日：2016-02-04

申请号：US14450145

申请日：2014-08-01

Applicant: Analog Devices Technology

Inventor： Abhijit Giri ,  Saurbh Srivastava ,  Michael S. Allen

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F2212/1024

Abstract: Digital signal processors often operate on two operands per instruction, and it is desirable to retrieve both operands in one cycle. Some data caches connect to the processor over two busses and internally uses two or more memory banks to store cache lines. The allocation of cache lines to specific banks is based on the address that the cache line is associated. When two memory accesses map to the same memory bank, fetching the operands incurs extra latency because the accesses are serialized. An improved bank organization for providing conflict-free dual-data cache access—a bus-based data cache system having two data buses and two memory banks—is disclosed. Each memory bank works as a default memory bank for the corresponding data bus. As long as the two values of data being accessed belong to two separate data sets assigned to the two respective data buses, memory bank conflicts are avoided.

Abstract translation: 数字信号处理器通常在每个指令的两个操作数上操作，并且期望在一个周期内检索两个操作数。 一些数据高速缓存通过两个总线连接到处理器，并且内部使用两个或多个存储体来存储高速缓存行。 将高速缓存行分配给特定存储区基于高速缓存行关联的地址。 当两个内存访问映射到同一个存储区时，获取操作数会导致额外的延迟，因为访问是序列化的。 公开了一种用于提供无冲突双数据高速缓存访​​问的改进的银行组织 - 具有两个数据总线和两个存储体的基于总线的数据高速缓存系统。 每个存储体都作为相应数据总线的默认存储体。 只要访问的数据的两个值属于分配给两个相应的数据总线的两个单独的数据集，就避免了存储体冲突。

公开(公告)号：US20150180485A1

公开(公告)日：2015-06-25

申请号：US14134767

申请日：2013-12-19

Applicant: Analog Devices Technology

Inventor： Hyman Shanan ,  Michael F. Keaveney

IPC: H03L7/099 ,  H03L7/093

CPC classification number: H03L7/099 ,  H03L1/026 ,  H03L7/104

Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.

Abstract translation: 提供了锁相环（PLL）的频率锁定增强的装置和方法。 在一个方面，PLL可以包括具有调谐电压输入的VCO和被配置为设置VCO的频带设置的频率调谐电路。 频率调谐电路可以包括电压监视器，其被配置为将调谐电压输入的电压电平与一个或多个调谐电压阈值电平进行比较，控制电路被配置为至少控制VCO的频带设置和偏置电流设置， 以及振幅检测电路，被配置为将VCO的振荡信号的振幅与一个或多个振幅阈值电平进行比较。

公开(公告)号：US20150171861A1

公开(公告)日：2015-06-18

申请号：US14109249

申请日：2013-12-17

Applicant: David AHERNE

Inventor： David AHERNE

IPC: H03K17/687

CPC classification number: H03K17/6872 ,  H03K2217/0018

Abstract: An analog switch may be maintained reliably in an off state. The switch comprises: a P-type first transistor having a source, a drain and a gate, a N-type second transistor having a source, a drain and a gate, and a switch control circuit to drive the gates of the first and second transistors. The drain of the first transistor and the source of the second transistor are connected at a first node, and the source of the first transistor and the drain of the second transistor are connected at a second node. When the voltage at the first or second nodes falls outside of a supply voltage range of the switch control circuit, the switch control circuit is operable, in response to a signal to make the switch high impedance, by adjusting the gate voltages of the first transistor and the second transistor.

Abstract translation: 可以将模拟开关可靠地维持在关闭状态。 开关包括：具有源极，漏极和栅极的P型第一晶体管，具有源极，漏极和栅极的N型第二晶体管，以及用于驱动第一和第二栅极的栅极的开关控制电路 晶体管。 第一晶体管的漏极和第二晶体管的源极连接在第一节点处，并且第一晶体管的源极和第二晶体管的漏极连接在第二节点处。 当第一或第二节点处的电压落在开关控制电路的电源电压范围之外时，开关控制电路可响应于使开关高阻抗的信号通过调节第一晶体管的栅极电压而工作 和第二晶体管。

公开(公告)号：US20150158114A1

公开(公告)日：2015-06-11

申请号：US14102132

申请日：2013-12-10

Applicant: Analog Devices Technology

Inventor： Bernard Patrick Stenson ,  Paul Martin Lambkin ,  Colette J. Blaney ,  John Beatty

IPC: B23K26/00 ,  H01L27/01

CPC classification number: H01G4/33 ,  H01C7/006 ,  H01C17/242 ,  H01G4/255

Abstract: A phase corrector for laser trimming a component, the phase corrector comprising: a first correction structure located to a first side of the component, the first correction structure comprising first and second correction regions at first and second distances from the component; and a second correction structure located to a second side the component, the second correction structure comprising third and fourth correction regions at third and fourth distances from the component.

Abstract translation: 一种用于激光微调分量的相位校正器，所述相位校正器包括：位于所述分量的第一侧的第一校正结构，所述第一校正结构包括距离所述分量的第一和第二距离处的第一和第二校正区域; 以及位于所述部件的第二侧的第二校正结构，所述第二校正结构包括距所述部件的第三和第四距离处的第三和第四校正区域。

公开(公告)号：US20150131705A1

公开(公告)日：2015-05-14

申请号：US14213561

申请日：2014-03-14

Applicant: Analog Devices Technology

Inventor： Haim Primo ,  Yosef Stein ,  Oz Gabai

IPC: H04B1/707

CPC classification number: H04B1/707

Abstract: A modulation scheme for long range transceiver utilizing a processing scheme in combination with a Hadamard transform is disclosed. The processing scheme can correspond to an industry standard or to other processing schemes. An input signal is parallelized through serial to parallel conversion. The processed parallel signals are orthogonalized using a Hadamard transform to allow multiple channel signals with increased throughput. Accordingly, the long range modulation scheme of this invention can achieve high efficiency and increased throughput while meeting performance goals of long range signal transmission.

Abstract translation: 公开了一种使用与Hadamard变换组合的处理方案的长距离收发机的调制方案。 处理方案可以对应于行业标准或其他处理方案。 输入信号通过串行到并行转换并行化。 使用Hadamard变换使处理的并行信号正交化，以允许具有增加的吞吐量的多个信道信号。 因此，本发明的长距离调制方案可以在满足长距离信号传输的性能目标的同时实现高效率和增加的吞吐量。

公开(公告)号：US20150116138A1

公开(公告)日：2015-04-30

申请号：US14065732

申请日：2013-10-29

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Zhao Li ,  David Alldred

IPC: H03M3/00

CPC classification number: H03M3/368 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30 ,  H03M3/38 ,  H03M3/424 ,  H03M3/454

Abstract: An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.

Abstract translation: 模数转换器（ADC）可以包括连续时间ΔΣ调制器和校准逻辑。 校准逻辑可以校准连续时间Δ-Σ调制器的直接反馈和闪速时钟延迟系数，而不中断ADC的正常操作（例如，原位）。 因此，校准逻辑可以通过校准次优系数来纠正性能和稳定性降级。

公开(公告)号：US20150102391A1

公开(公告)日：2015-04-16

申请号：US14055738

申请日：2013-10-16

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Edward John Coyne

IPC: H01L29/808 ,  H01L29/66

CPC classification number: H01L29/808 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/66893 ,  H01L29/66901

Abstract: A method of forming a junction field effect transistor, the transistor comprising: a back gate; a channel; a top gate; a drain and a source in current flow with the channel; wherein the method comprises selecting a first channel dimension between the top gate and the back gate such that a significant current flow path in the channel occurs in a region of relatively low electric field strength.

Abstract translation: 一种形成结型场效应晶体管的方法，所述晶体管包括：背栅极; 一个渠道 顶门 电流与通道的漏极和源极; 其中所述方法包括选择所述顶栅极和所述后栅极之间的第一沟道尺寸，使得所述沟道中的有效电流流动路径发生在相对低的电场强度的区域中。

公开(公告)号：US08994564B2

公开(公告)日：2015-03-31

申请号：US14016787

申请日：2013-09-03

Applicant: Christopher Peter Hurrell ,  Derek Hummerstone ,  Meabh Shine

Inventor： Christopher Peter Hurrell ,  Derek Hummerstone ,  Meabh Shine

IPC: H03M1/12 ,  G11C27/02 ,  H03K17/687

CPC classification number: H03M1/1245 ,  G11C27/02 ,  H03K17/687 ,  H03M1/12 ,  H03M1/1225

Abstract: An analog to digital converter comprising at least one sampling capacitor connected to a sample node, and a pre-charge circuit arranged to cause the voltage on the sample node to substantially match the input voltage prior to the analog to digital converter entering an acquire mode in which the sample node is connected to the input node by a sample switch.

Abstract translation: 一种模数转换器，包括连接到采样节点的至少一个采样电容器和预充电电路，该预充电电路被布置成使得在模数转换器进入采集模式之前使样本节点上的电压基本匹配输入电压 样本节点通过采样开关连接到输入节点。

公开(公告)号：US20150073739A1

公开(公告)日：2015-03-12

申请号：US14020404

申请日：2013-09-06

Applicant: Analog Devices Technology

Inventor： Muhammad Kalimuddin Khan ,  Kenneth J. Mulvaney ,  Michale Deeney ,  Niall Kevin Kearney

IPC: G01R23/02

CPC classification number: G01R23/02 ,  H03L7/095 ,  H03L7/193 ,  H03L7/1974 ,  H03L7/1976

Abstract: A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.

Abstract translation: 一种用于监视其中具有分频器的锁相环的性能的监视电路，所述分频器包括至少第一计数器，所述分频器包括至少一个存储器元件，用于在来自系统的预定时间之后捕获所述第一计数器的值 可变性计算器，用于将计数器的值与计数器的先前值进行比较以计算变化;以及电路，其响应于用于输出状态信号的变化估计。

公开(公告)号：US08965132B2

公开(公告)日：2015-02-24

申请号：US13426844

申请日：2012-03-22

Applicant: Bijesh Poyil ,  Anil Sripadarao

Inventor： Bijesh Poyil ,  Anil Sripadarao

IPC: G06K9/48 ,  G06T7/00

CPC classification number: G06T7/0085 ,  G06T7/13 ,  G06T7/181 ,  G06T7/187 ,  G06T2207/20072

Abstract: A method for tracing edges of an image using hysteresis thresholding includes: (i) receiving an edge map of the image, (ii) scanning one row of the input edge map, (iii) assigning a label to each edge pixel in the row based at least in part on the presence or absence of a neighboring edge pixel, (iv) grouping contiguous labels, and (v) identifying groups of edge pixels.

Abstract translation: 使用滞后阈值跟踪图像边缘的方法包括：（i）接收图像的边缘图，（ii）扫描输入边缘图的一行，（iii）为行中的每个边缘像素分配标签 至少部分地基于相邻边缘像素的存在或不存在，（iv）对相邻标签进行分组，以及（v）识别边缘像素组。