公开(公告)号：US10147796B1

公开(公告)日：2018-12-04

申请号：US15606778

申请日：2017-05-26

Applicant: STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

Inventor： Patrik Vacula ,  Milos Vacula ,  Vlastimil Kote ,  Adam Kubacak ,  Milan Lzicar

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure is directed to a plurality of waffle gate parallel transistors having a shared gate on a surface of a semiconductor substrate. The shared gate has connected channels that form a plurality of squares, lines of each of the squares over the perimeter of a respective source or drain region of the plurality of waffle gate parallel transistors. The shared gate includes squares of a first size and shape and a second size and shape. The squares having the first size and shape are each over a respective source region and the squares having the second size and shape are each over a respective drain region. Each of the squares having a first size and shape share at least one side with one of the squares having the second size and shape.

公开(公告)号：US09864395B1

公开(公告)日：2018-01-09

申请号：US15367628

申请日：2016-12-02

Applicant: STMicroelectronics Design and Application S.R.O ,  STMicroelectronics Asia Pacific Pte Ltd

Inventor： Roman Prochazka ,  Chee Weng Cheong

IPC: G05F3/26

CPC classification number: G05F3/267

Abstract: A current mirror circuit includes an input current leg and an output current leg. The input current leg includes: a first bipolar junction transistor (BJT) having a collector terminal configured to receive an input current sourced at a current node and a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal coupled to the current node and a source terminal coupled to a base terminal of the first BJT. The output current leg includes: a second BJT having a collector terminal configured to supply an output current and a second MOSFET having a gate terminal coupled to the current node and a source terminal coupled to a base terminal of the second BJT.

公开(公告)号：US09691493B1

公开(公告)日：2017-06-27

申请号：US15244664

申请日：2016-08-23

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Design & Application S.R.O.

Inventor： Marco Pasotti ,  Fabio De Santis ,  Roberto Bregoli ,  Dario Livornesi ,  Sandor Petenyi

IPC: G11C16/10 ,  G11C16/30 ,  H01L27/11521 ,  G11C16/28 ,  G11C16/04 ,  G11C5/14

CPC classification number: G11C16/30 ,  G05F3/30 ,  G11C5/147 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/1156 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/456 ,  H03F2203/45341 ,  H03F2203/45342 ,  H03F2203/45528 ,  H03F2203/45674 ,  H03F2203/45676

Abstract: A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.

公开(公告)号：US09176567B2

公开(公告)日：2015-11-03

申请号：US13904866

申请日：2013-05-29

Applicant: STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Christophe Lorin ,  Benedicte Micheau ,  Roman Prochazka ,  Vaclav Jelen ,  Ondrej Plachy

IPC: G06F1/00 ,  G06F1/26 ,  H02J7/00 ,  H02J7/04 ,  G06F3/00 ,  G06F1/32

CPC classification number: H02J7/0054 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3215 ,  G06F1/3234 ,  G06F1/3246 ,  G06F1/3287 ,  H02J7/0047 ,  H02J7/007 ,  H02J7/345 ,  H02J2007/0049 ,  H02J2007/0062

Abstract: A method of charging a battery of a device using a battery of a computer powered by the battery, in which the procedure is implemented by a circuit independent of the computer's processors. The method includes supplying a power supply voltage, insufficient to charge a battery, to a computer port, as long as a device is detected as connected to the port, controlling the supply of a charging voltage to the port, while supplying charging voltage to the port, detecting an end of charging condition of a battery of the device, and controlling the cutting off of the charging voltage to the port if the end of charging condition is detected, where this condition is determined according to the intensity of a charging current and according to a quantity of electrical charge supplied to the port and/or of a charging period.

Abstract translation: 一种使用由电池供电的计算机的电池对装置的电池进行充电的方法，其中该过程由独立于计算机的处理器的电路实现。 该方法包括向计算机端口提供不足以对电池充电的电源电压，只要检测到设备连接到端口，控制向端口提供充电电压，同时向该端口提供充电电压 端口，检测设备的电池的充电状态的结束，并且如果检测到充电状态的结束，则控制对端口的充电电压的切断，其中该条件根据充电电流的强度确定，并且 根据提供给端口的电量和/或充电期间。

公开(公告)号：US09035639B2

公开(公告)日：2015-05-19

申请号：US13711454

申请日：2012-12-11

Applicant: STMicroelectronics Design and Application S.R.O.

Inventor： Martin Drinovsky

IPC: G05F1/00 ,  G05F1/46 ,  G05F1/56 ,  H02M3/156 ,  H02M1/00

CPC classification number: G05F1/46 ,  G05F1/561 ,  H02M3/156 ,  H02M2001/0009

Abstract: The present disclosure is directed to a voltage-to-current sensing circuit having a bias terminal configured to receive a reference voltage, an offset terminal configured to receive an offset current, and an operational amplifier configured to output a low voltage signal. The device includes a first amplifier having first and second high voltage inputs configured to receive a first voltage difference across a sense component on a high voltage line and to generate a first current, a second amplifier having first and second low voltage inputs configured to receive a second voltage difference between the bias terminal and the offset terminal and to generate a second current, a summing circuit configured to provide an intermediate voltage corresponding to a sum of the first and the second currents, and a low-voltage transistor coupled to an output of the amplifier and controlled by the intermediate voltage to generate the output current.

Abstract translation: 本公开涉及具有被配置为接收参考电压的偏置端子的电压到电流感测电路，被配置为接收偏移电流的偏移端子和被配置为输出低电压信号的运算放大器。 该器件包括具有第一和第二高电压输入的第一放大器，该第一和第二高电压输入被配置为接收高电压线上的感测元件上的第一电压差并产生第一电流，第二放大器具有第一和第二低电压输入， 偏置端子和偏移端子之间的第二电压差并产生第二电流，求和电路被配置为提供对应于第一和第二电流的和的中间电压，以及耦合到第一和第二电流的输出的低压晶体管 该放大器由中间电压控制，以产生输出电流。

公开(公告)号：US08674615B2

公开(公告)日：2014-03-18

申请号：US13346531

申请日：2012-01-09

Applicant: Pavel Koutensky ,  Ales Loidl ,  Jiri Smutka ,  Jakub Hajek

Inventor： Pavel Koutensky ,  Ales Loidl ,  Jiri Smutka ,  Jakub Hajek

IPC: H05B37/00

CPC classification number: H05B33/0815 ,  H05B33/0818 ,  H05B33/0851 ,  Y02B20/383

Abstract: A control apparatus for LED diodes includes a dimmer TRIAC electrically connected in series between a power supply and a LED lighting converter. The converter comprises a transformer, with a primary winding coupled with an input terminal and a secondary winding coupled with an output terminal, and a switch coupled to the primary winding to regulate the current through the primary winding and regulate the output voltage. The apparatus comprises a control device adapted to control said switch determining the on period and the off period of the switch to maintain constant the output current to supply said LED diodes. The apparatus comprises a detector connected to the secondary winding of the transformer and adapted to detect the conduction angle of the TRIAC; the control device is adapted to regulate the output current to supply said LED diodes in response to the TRIAC conduction angle detected by the detector.

Abstract translation: 用于LED二极管的控制装置包括电源和LED照明转换器之间串联电连接的调光器TRIAC。 该转换器包括一个变压器，一个初级绕组与一个输入端子耦合，一个次级绕组与一个输出端子耦合，一个开关耦合到初级绕组，以调节通过初级绕组的电流并调节输出电压。 该装置包括控制装置，其适于控制所述开关确定开关的导通周期和关断周期以保持输出电流恒定以供应所述LED二极管。 该装置包括检测器，连接到变压器的次级绕组并适于检测TRIAC的导通角; 控制装置适于调节输出电流以响应由检测器检测到的TRIAC导通角来供应所述LED二极管。

公开(公告)号：US20130154595A1

公开(公告)日：2013-06-20

申请号：US13711454

申请日：2012-12-11

Applicant: STMicroelectronics Design and Application S.R.O

Inventor： Martin Drinovsky

IPC: G05F1/46

CPC classification number: G05F1/46 ,  G05F1/561 ,  H02M3/156 ,  H02M2001/0009

Abstract: The present disclosure is directed to a voltage-to-current sensing circuit having a bias terminal configured to receive a reference voltage, an offset terminal configured to receive an offset current, and an operational amplifier configured to output a low voltage signal. The device includes a first amplifier having first and second high voltage inputs configured to receive a first voltage difference across a sense component on a high voltage line and to generate a first current, a second amplifier having first and second low voltage inputs configured to receive a second voltage difference between the bias terminal and the offset terminal and to generate a second current, a summing circuit configured to provide an intermediate voltage corresponding to a sum of the first and the second currents, and a low-voltage transistor coupled to an output of the amplifier and controlled by the intermediate voltage to generate the output current.

Abstract translation: 本公开涉及具有被配置为接收参考电压的偏置端子的电压到电流感测电路，被配置为接收偏移电流的偏移端子和被配置为输出低电压信号的运算放大器。 该器件包括具有第一和第二高电压输入的第一放大器，该第一和第二高电压输入被配置为接收高电压线上的感测元件上的第一电压差并产生第一电流，第二放大器具有第一和第二低电压输入， 偏置端子和偏移端子之间的第二电压差并产生第二电流，求和电路被配置为提供对应于第一和第二电流的和的中间电压，以及耦合到第一和第二电流的输出的低压晶体管 该放大器由中间电压控制，以产生输出电流。

公开(公告)号：US08403648B2

公开(公告)日：2013-03-26

申请号：US12016287

申请日：2008-01-18

Applicant: Albert Boscarato

Inventor： Albert Boscarato

IPC: F04B49/06

CPC classification number: F04B49/10 ,  F04B49/02 ,  F04B2203/0205 ,  F25B49/025 ,  F25B2500/26 ,  F25B2700/151

Abstract: A compressor control device includes a driving circuit, for controllably supplying a coil of an electric motor of a compressor. A temperature sensor is thermally coupled to the driving circuit and provides a temperature sensing signal correlated to a temperature in the driving circuit. A control stage, coupled to the driving circuit and to the temperature sensor, selectively prevents the driving circuit from supplying the coil, in response to a minimum temperature increment being detected by the temperature sensor within a pre-determined control time window.

Abstract translation: 压缩机控制装置包括用于可控地供应压缩机的电动机的线圈的驱动电路。 温度传感器热耦合到驱动电路并且提供与驱动电路中的温度相关的温度感测信号。 响应于温度传感器在预定的控制时间窗口内检测到的最小温度增量，耦合到驱动电路和温度传感器的控制级选择性地防止驱动电路供应线圈。

公开(公告)号：US08058926B2

公开(公告)日：2011-11-15

申请号：US11655727

申请日：2007-01-19

Applicant: Hynek Saman ,  Peter Murin ,  Martin Boksa ,  Pavel Panus

Inventor： Hynek Saman ,  Peter Murin ,  Martin Boksa ,  Pavel Panus

IPC: G06G7/12

CPC classification number: H03F1/30 ,  H03F1/26 ,  H03F3/45475 ,  H03F3/45632 ,  H03F3/72 ,  H03F2200/372 ,  H03F2200/459 ,  H03F2203/45534

Abstract: A switch including a first transistor including a first main terminal connected to a first switch node, a second main terminal connected to a second switch node and a control terminal, the second switch node being connected to a first clean voltage supply, and first control circuitry connected to the control terminal of the first transistor, including a first node connected to the first clean voltage supply, a second node connected to a second voltage level, and a control input node for receiving a first input control signal variable between a supply voltage level and a third voltage level, the first control means arranged to selectively connect the control terminal of the first transistor to one of the first node and the second node based on the first input control signal.

Abstract translation: 一种开关，包括第一晶体管，包括连接到第一开关节点的第一主端子，连接到第二开关节点的第二主端子和控制端子，所述第二开关节点连接到第一清洁电压源，以及第一控制电路 连接到第一晶体管的控制端子，包括连接到第一清洁电压源的第一节点，连接到第二电压电平的第二节点和控制输入节点，用于接收电源电压等级之间的第一输入控制信号变量 和第三电压电平，所述第一控制装置被布置成基于所述第一输入控制信号选择性地将所述第一晶体管的控制端子连接到所述第一节点和所述第二节点之一。

公开(公告)号：US08040172B2

公开(公告)日：2011-10-18

申请号：US12621380

申请日：2009-11-18

Applicant: Tomas Jerabek ,  Karel Napravnik

Inventor： Tomas Jerabek ,  Karel Napravnik

IPC: H03H11/16

CPC classification number: H03K19/018521 ,  H03K3/356113

Abstract: A logic level converter includes two first electronic switches coupled in a bi-stable flip-flop arrangement having at least one output line, and a forcing circuitry including two second electronic switches to force switching of the first electronic switches in the flip-flop arrangement. The forcing circuitry has an input terminal to receive a logic input signal having a given level to produce switching of the flip-flop arrangement and generate at the output line(s) of the flip-flop arrangement, a logic output signal(s) whose voltage level is converted with respect to the level of the logic input signal. The converter includes, interposed between each of the two first electronic switches in the flip-flop arrangement and a respective one of the second electronic switches in the forcing circuitry, at least one respective cascode electronic switch to limit the voltage across the two first electronic switches in the flip-flop arrangement.

Abstract translation: 逻辑电平转换器包括耦合在具有至少一个输出线的双稳态触发器装置中的两个第一电子开关，以及包括两个第二电子开关以强制在触发器装置中切换第一电子开关的强制电路。 强制电路具有用于接收具有给定电平的逻辑输入信号的输入端以产生触发器装置的切换并在触发器装置的输出线处产生逻辑输出信号，其逻辑输出信号 电压电平相对于逻辑输入信号的电平被转换。 转换器包括插入在触发器装置中的两个第一电子开关中的每一个和强制电路中的相应一个第二电子开关中的至少一个相应的共源共栅电子开关以限制两个第一电子开关 在触发器安排。