公开(公告)号：US08912890B2

公开(公告)日：2014-12-16

申请号：US13632745

申请日：2012-10-01

Applicant: Patrick Smith ,  Criswell Choi ,  James Montague Cleeves ,  Vivek Subramanian ,  Arvind Kamath ,  Steven Molesa

Inventor： Patrick Smith ,  Criswell Choi ,  James Montague Cleeves ,  Vivek Subramanian ,  Arvind Kamath ,  Steven Molesa

IPC: H04Q5/22

CPC classification number: H01G4/40 ,  H01G4/38

Abstract: The disclosure relates to surveillance and/or identification devices having capacitors connected in parallel or in series, and methods of making and using such devices. Devices with capacitors connected in parallel, where one capacitor is fabricated with a relatively thick capacitor dielectric and another is fabricated with a relatively thin capacitor dielectric achieve both a high-precision capacitance and a low breakdown voltage for relatively easy surveillance tag deactivation. Devices with capacitors connected in series result in increased lateral dimensions of a small capacitor. This makes the capacitor easier to fabricate using techniques that may have relatively limited resolution capabilities.

Abstract translation: 本公开涉及具有并联或串联连接的电容器的监视和/或识别装置以及制造和使用这些装置的方法。 具有并联连接电容器的器件，其中一个电容器用相对较厚的电容器电介质制造，另一个电容器由相对薄的电容器电介质制成，实现了高精度电容和低击穿电压，以便相对容易的监视标签去激活。 具有串联连接的电容器的装置增加了小电容器的横向尺寸。 这使得使用可能具有相对有限的分辨能力的技术来制造电容器更容易。

公开(公告)号：US08822301B2

公开(公告)日：2014-09-02

申请号：US13791721

申请日：2013-03-08

Applicant: Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

Inventor： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

IPC: H01L21/20

CPC classification number: H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

Abstract translation: 本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法 通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。 平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。 本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。 这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。 均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

公开(公告)号：US20130344301A1

公开(公告)日：2013-12-26

申请号：US13975231

申请日：2013-08-23

Applicant: Erik SCHER ,  Steven MOLESA ,  Joerg ROCKENBERGER ,  Arvind KAMATH ,  Ikuo MORI ,  Wenzhuo GUO ,  Dmitry KARSHTEDT ,  Vladimir DIOUMAEV

Inventor： Erik SCHER ,  Steven MOLESA ,  Joerg ROCKENBERGER ,  Arvind KAMATH ,  Ikuo MORI ,  Wenzhuo GUO ,  Dmitry KARSHTEDT ,  Vladimir DIOUMAEV

IPC: C09D5/24 ,  H01B3/02

CPC classification number: C09D5/24 ,  C09D11/101 ,  C09D11/322 ,  C09D11/36 ,  C09D11/54 ,  H01B3/02 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28008 ,  H01L27/1292 ,  H01L29/6675 ,  H01L29/78696 ,  Y10T428/24802

Abstract: Embodiments relate to printing features from an ink containing a material precursor. In some embodiments, the material includes an electrically active material, such as a semiconductor, a metal, or a combination thereof. In another embodiment, the material includes a dielectric. The embodiments provide improved printing process conditions that allow for more precise control of the shape, profile and dimensions of a printed line or other feature. The composition(s) and/or method(s) improve control of pinning by increasing the viscosity and mass loading of components in the ink. An exemplary method thus includes printing an ink comprising a material precursor and a solvent in a pattern on the substrate; precipitating the precursor in the pattern to form a pinning line; substantially evaporating the solvent to form a feature of the material precursor defined by the pinning line; and converting the material precursor to the patterned material.

Abstract translation: 实施例涉及从含有材​​料前体的油墨印刷特征。 在一些实施例中，材料包括电活性材料，例如半导体，金属或其组合。 在另一个实施例中，该材料包括电介质。 这些实施例提供改进的印刷工艺条件，其允许更精确地控制印刷线或其它特征的形状，轮廓和尺寸。 组合物和/或方法通过增加油墨中组分的粘度和质量负载来改善对钉扎的控制。 因此，示例性方法包括在基板上以图案印刷包含材料前体和溶剂的油墨; 以图案沉淀前体以形成钉扎线; 基本上蒸发溶剂以形成由钉扎线限定的材料前体的特征; 并将材料前体转化成图案化材料。

公开(公告)号：US08460983B1

公开(公告)日：2013-06-11

申请号：US12357065

申请日：2009-01-21

Applicant: Wenzhuo Guo ,  Fabio Zürcher ,  Arvind Kamath ,  Joerg Rockenberger

Inventor： Wenzhuo Guo ,  Fabio Zürcher ,  Arvind Kamath ,  Joerg Rockenberger

IPC: C09D183/16 ,  H01L21/208

CPC classification number: H01L21/02667 ,  C08G77/56 ,  C08K5/55 ,  C08K2201/001 ,  C09D11/52 ,  C09D183/16 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02628 ,  H01L21/208 ,  H01L27/1292 ,  H01L29/167 ,  H01L29/66757

Abstract: Doped semiconductor ink formulations, methods of making doped semiconductor ink formulations, methods of coating or printing thin films, methods of forming electronic devices and/or structures from the thin films, and methods for modifying and controlling the threshold voltage of a thin film transistor using the films are disclosed. A desired dopant may be added to an ink formulation comprising a Group IVA compound and a solvent, and then the ink may be printed on a substrate to form thin films and conductive structures/devices, such as thin film transistors. By adding a customized amount of the dopant to the ink prior to printing, the threshold voltage of a thin film transistor made from the doped semiconductor ink may be independently controlled upon activation of the dopant.

Abstract translation: 掺杂的半导体油墨配方，制造掺杂的半导体油墨配方的方法，涂覆或印刷薄膜的方法，从薄膜形成电子器件和/或结构的方法，以及用于修改和控制薄膜晶体管的阈值电压的方法，其使用 披露了这些电影。 可以将期望的掺杂剂添加到包含IVA族化合物和溶剂的油墨配方中，然后可以将油墨印刷在基材上以形成薄膜和诸如薄膜晶体管的导电结构/器件。 通过在打印之前向墨水添加定制量的掺杂剂，可以在掺杂剂激活时独立地控制由掺杂半导体油墨制成的薄膜晶体管的阈值电压。

公开(公告)号：US08446706B1

公开(公告)日：2013-05-21

申请号：US12249841

申请日：2008-10-10

Applicant: Arvind Kamath ,  Criswell Choi ,  Patrick Smith ,  Erik Scher ,  Jiang Li

Inventor： Arvind Kamath ,  Criswell Choi ,  Patrick Smith ,  Erik Scher ,  Jiang Li

IPC: H01G4/06 ,  H01G4/005

CPC classification number: H01G4/40 ,  H01G4/002 ,  H01G4/005 ,  H01G4/008 ,  H01G4/01 ,  H01G4/10 ,  H01G4/1209 ,  H01G4/224 ,  H01G4/30 ,  H01G4/306 ,  H01G4/33 ,  H01G13/00 ,  H01L23/66 ,  H01L27/016 ,  H01L28/60 ,  H01L2223/6677 ,  H01Q1/22 ,  H01Q1/2283 ,  H01Q1/38 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49016

Abstract: High precision capacitors and methods for forming the same utilizing a precise and highly conformal deposition process for depositing an insulating layer on substrates of various roughness and composition. The method generally comprises the steps of depositing a first insulating layer on a metal substrate by atomic layer deposition (ALD); (b) forming a first capacitor electrode on the first insulating layer; and (c) forming a second insulating layer on the first insulating layer and on or adjacent to the first capacitor electrode. Embodiments provide an improved deposition process that produces a highly conformal insulating layer on a wide range of substrates, and thereby, an improved capacitor.

Abstract translation: 高精度电容器及其形成方法采用精确且高度保形的沉积工艺，用于在各种粗糙度和组成的基底上沉积绝缘层。 该方法通常包括以下步骤：通过原子层沉积（ALD）在金属衬底上沉积第一绝缘层; （b）在所述第一绝缘层上形成第一电容器电极; 和（c）在所述第一绝缘层上形成第二绝缘层，并且在所述第一电容器电极上或与所述第一电容器电极相邻。 实施例提供了一种改进的沉积工艺，其在宽范围的衬底上产生高度保形的绝缘层，从而产生改进的电容器。

公开(公告)号：US08264027B2

公开(公告)日：2012-09-11

申请号：US12723542

申请日：2010-03-12

Applicant: Arvind Kamath ,  Patrick Smith ,  James Montague Cleeves

Inventor： Arvind Kamath ,  Patrick Smith ,  James Montague Cleeves

IPC: H01L29/788

CPC classification number: H01L21/28518 ,  H01L21/288 ,  H01L21/76801 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11558 ,  H01L27/1292 ,  H01L29/66757 ,  H01L29/66825 ,  H01L29/7881

Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.

Abstract translation: 公开了一种非易失性存储器单元，其具有在相同水平位置处并且间隔开预定距离的第一和第二半导体岛，所述第一半岛具有提供控制栅极和所述第二半岛岛提供源极和漏极端子; 在所述第一半导体岛的至少一部分上的栅介质层; 在所述第二半导体岛的至少一部分上的隧道介电层; 至少部分栅极电介质层和隧道电介质层上的浮栅; 以及与控制栅极以及源极和漏极端子电接触的金属层。 在一个有利的实施例中，可以使用“全印刷”工艺技术来制造非易失性存储单元。

公开(公告)号：US08158518B2

公开(公告)日：2012-04-17

申请号：US12175450

申请日：2008-07-17

Applicant: Aditi Chandra ,  Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Mao Takashima ,  Erik Scher

Inventor： Aditi Chandra ,  Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Mao Takashima ,  Erik Scher

IPC: H01L21/44

CPC classification number: H01L21/288 ,  H01L21/28518 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76873 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L29/458 ,  H01L29/78618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. The method of forming contacts includes depositing an ink of a silicide-forming metal onto an exposed silicon surface, drying the ink to form a silicide-forming metal precursor, and heating the silicide-forming metal precursor and the silicon surface to form a metal silicide contact. Optionally, the metal precursor ink may be selectively deposited onto a dielectric layer adjacent to the exposed silicon surface to form a metal-containing interconnect. Furthermore, one or more bulk conductive metal(s) may be deposited on remaining metal precursor ink and/or the dielectric layer. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching.

Abstract translation: 公开了使用包含硅化物形成金属的油墨形成触点（和任选的局部互连）的方法，诸如二极管和/或包括这种触点的晶体管的电气器件，（可选的）局部互连）以及用于形成这种器件的方法。 形成接触的方法包括将硅化物形成金属的油墨沉积到暴露的硅表面上，干燥油墨以形成形成硅化物的金属前体，以及加热形成硅化物的金属前体和硅表面以形成金属硅化物 联系。 任选地，可以将金属前体油墨选择性地沉积到与暴露的硅表面相邻的电介质层上，以形成含金属互连。 此外，一个或多个体导电金属可以沉积在剩余的金属前体油墨和/或介电层上。 可以使用这种印刷的接触和/或局部互连来制造电子器件，例如二极管和晶体管。 金属墨水可以同时印刷以用于接触以及局部互连，或者替代地，如果需要用于接触和互连线的不同金属，印刷金属可以用作其它金属的无电沉积的种子 。 这种方法有利地减少了处理步骤的数量，并且不一定需要任何蚀刻。

公开(公告)号：US08021955B1

公开(公告)日：2011-09-20

申请号：US12574426

申请日：2009-10-06

Applicant: Venkatesh P. Gopinath ,  Arvind Kamath ,  Mohammad R. Mirabedini ,  Ming-Yi Lee

Inventor： Venkatesh P. Gopinath ,  Arvind Kamath ,  Mohammad R. Mirabedini ,  Ming-Yi Lee

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.

Abstract translation: 提供了用于在集成电路基板上形成多层隔离结构的方法和组合物。 工艺可以包括为下电介质层选择下电介质材料，并选择用于上电介质层的上电介质材料。 选择对应于下部和上部介电材料的厚度的一系列有效介电常数。 下介电层和上电介质层中的每一个的厚度范围由可接受的介电常数的范围决定，使用表示与下部上部电介质层的材料的厚度对应的有效介电常数的信息，能够形成多层电介质层， 层隔离结构。

公开(公告)号：US20080048240A1

公开(公告)日：2008-02-28

申请号：US11842884

申请日：2007-08-21

Applicant: Arvind Kamath ,  Patrick Smith ,  James Montague Cleeves

Inventor： Arvind Kamath ,  Patrick Smith ,  James Montague Cleeves

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L21/28518 ,  H01L21/288 ,  H01L21/76801 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11558 ,  H01L27/1292 ,  H01L29/66757 ,  H01L29/66825 ,  H01L29/7881

Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.

Abstract translation: 公开了一种非易失性存储器单元，其具有在相同水平位置处并且间隔开预定距离的第一和第二半导体岛，所述第一半岛具有提供控制栅极和所述第二半岛岛提供源极和漏极端子; 在所述第一半导体岛的至少一部分上的栅介质层; 在所述第二半导体岛的至少一部分上的隧道介电层; 至少部分栅极电介质层和隧道电介质层上的浮栅; 以及与控制栅极以及源极和漏极端子电接触的金属层。 在一个有利的实施例中，可以使用“全印刷”工艺技术来制造非易失性存储单元。

公开(公告)号：US20080044964A1

公开(公告)日：2008-02-21

申请号：US11888949

申请日：2007-08-03

Applicant: Arvind Kamath ,  James Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zurcher

Inventor： Arvind Kamath ,  James Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zurcher

IPC: H01L21/00 ,  H01L21/311

CPC classification number: H01L21/316 ,  H01L21/02211 ,  H01L21/02288 ,  H01L21/02318 ,  H01L21/3165 ,  H01L27/1285 ,  H01L27/1292 ,  H01L29/66757 ,  H01L29/78621

Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

Abstract translation: 一种用于制造诸如MOS晶体管的电子器件的方法，包括以下步骤：在电功能衬底上形成多个半导体岛，在第一半导体岛子集上或第二子体上印刷第一电介质层， 在半导体岛的第二子集上或之上，以及退火。 第一介电层包含第一掺杂剂，并且（任选的）第二介电层包含不同于第一掺杂剂的第二掺杂剂。 电介质层，半导体岛和衬底被充分退火以将第一掺杂剂扩散到半导体岛的第一子集中，并且当存在时将第二掺杂剂扩散到半导体岛的第二子集中。