公开(公告)号：US20050255642A1

公开(公告)日：2005-11-17

申请号：US10842454

申请日：2004-05-11

申请人： Chi-Wen Liu ,  Jung-Chih Tsao

发明人： Chi-Wen Liu ,  Jung-Chih Tsao

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/336 ,  H01L21/338 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/49

CPC分类号： H01L21/76885 ,  H01L21/28079 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/7684 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66583

摘要： A method of fabricating an inlaid structure. A sacrificial layer having a trench opening over a substrate is provided. A metal layer is deposited over the sacrificial layer filling the trench openings. A first CMP is performed to remove excess metal layer above the sacrificial layer to form an interconnect structure. The sacrificial layer is removed to expose the interconnect structure. A first dielectric layer is deposited over the substrate covering the interconnect structure. A second CMP is performed on the first dielectric layer to planarize the first dielectric layer.

摘要翻译： 一种制造镶嵌结构的方法。 提供了在衬底上具有沟槽开口的牺牲层。 在填充沟槽开口的牺牲层上沉积金属层。 执行第一CMP以去除牺牲层上方的多余金属层以形成互连结构。 去除牺牲层以露出互连结构。 在覆盖互连结构的衬底上沉积第一介电层。 在第一电介质层上执行第二CMP以使第一电介质层平坦化。

公开(公告)号：US20050118808A1

公开(公告)日：2005-06-02

申请号：US10724201

申请日：2003-12-01

申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

IPC分类号： H01L21/302 ,  H01L21/321 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/3212 ,  H01L21/7684

摘要： A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

摘要翻译： 降低CMP工艺中图案效果的方法。 该方法包括以下步骤：提供具有图案化介电层的半导体衬底，图案化电介质层上的阻挡层和阻挡层上的导电层; 在阻挡层被抛光之前执行第一CMP工艺以去除导电层的一部分，从而降低导电层的台阶高度; 在导电层上沉积与导电层基本相同的材料层; 以及执行第二CMP工艺以暴露所述电介质层。 还提供了在CMP处理和CMP返工方法之后消除凹陷现象的方法。

公开(公告)号：US06825120B1

公开(公告)日：2004-11-30

申请号：US10176855

申请日：2002-06-21

申请人： Chi-Wen Liu ,  Ying-Lang Wang

发明人： Chi-Wen Liu ,  Ying-Lang Wang

IPC分类号： H01L21461

CPC分类号： H01L21/76877 ,  H01L21/7684

摘要： The present invention relates to a method of protecting a fresh metal surface, preferably copper, after a metal deposition step. The metal deposition is preferably part of single or dual damascene process. The metal surface is treated with an amine, preferably BTA, to form a metal complex that is a hydrophobic monolayer and prevents the underlying metal from reacting to form oxides that can degrade device performance. The amine can be applied in various ways including dipping, spraying, spin coating, and by a CVD method. The sacrificial protective layer can remain on the substrate during a storage period of up to hours or days before it is removed in a subsequent chemical mechanical polish step. The use of a sacrificial protective layer improves throughput in a damascene process by allowing long queue times between metal deposition and CMP which gives more flexibility to production flow and reduces cost.

摘要翻译： 本发明涉及在金属沉积步骤之后保护新鲜金属表面，优选铜的方法。 金属沉积优选是单镶嵌或双镶嵌工艺的一部分。 用胺（优选BTA）处理金属表面以形成作为疏水性单层的金属络合物，并防止下面的金属反应形成可能降低器件性能的氧化物。 胺可以以各种方式施用，包括浸渍，喷涂，旋涂和通过CVD方法。 在后续化学机械抛光步骤中除去之前，牺牲保护层可以在高达数小时或数天的储存期间保留在基材上。 牺牲保护层的使用通过允许金属沉积和CMP之间的长队列时间来提高镶嵌工艺中的生产率，这为生产流程提供了更大的灵活性并降低了成本。

公开(公告)号：US06673661B1

公开(公告)日：2004-01-06

申请号：US10324965

申请日：2002-12-20

申请人： Chi-Wen Liu ,  Ting-Chang Chang ,  Po-Tsun Liu ,  Ying-Lang Wang

发明人： Chi-Wen Liu ,  Ting-Chang Chang ,  Po-Tsun Liu ,  Ying-Lang Wang

IPC分类号： H01L2184

CPC分类号： H01L29/6675 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78684

摘要： A method for fabricating a dual gate thin film transistor (TFT) device provides for forming a pair of source/drain layers self-aligned with respect to a first gate electrode and forming a second gate electrode self-aligned with respect to both the pair of source/drain layers and the first gate electrode. Thus, the dual gate TFT device is fabricated with enhanced alignment. In addition, the dual gate TFT device (or a single gate TFT device) may be fabricated with source/drain layers formed of a silicon-germanium alloy material, such as to provide the TFT device with enhanced performance with respect to a kink effect.

摘要翻译： 制造双栅极薄膜晶体管（TFT）器件的方法提供了形成相对于第一栅极电极自对准的一对源极/漏极层，并且形成相对于所述一对栅极电极自对准的第二栅电极 源极/漏极层和第一栅极电极。 因此，双栅极TFT器件被制造成具有增强的对准。 此外，双栅极TFT器件（或单栅极TFT器件）可以由硅 - 锗合金材料形成的源极/漏极层制造，以提供相对于扭结效应具有增强性能的TFT器件。

公开(公告)号：US06670274B1

公开(公告)日：2003-12-30

申请号：US10261967

申请日：2002-10-01

申请人： Chi-Wen Liu ,  Ying-Lang Wang

发明人： Chi-Wen Liu ,  Ying-Lang Wang

IPC分类号： H01L21302

CPC分类号： H01L21/02068 ,  H01L21/32134 ,  H01L21/76849

摘要： A method of forming a planarized final copper structure including the following steps. A structure is provided having a patterned dielectric layer formed thereover. The patterned dielectric layer having an opening formed therein. A barrier layer is formed over the patterned dielectric layer, lining the opening. An initial planarized copper structure is formed within the barrier layer lined opening, and is planar with the barrier layer overlying the patterned dielectric layer. The initial planarized copper structure is recessed below the barrier layer overlying the patterned dielectric layer a distance to form a recessed copper structure. Any copper oxide formed upon the recessed copper structure is removed. A conductor film is formed over the recessed, copper oxide-free initial copper structure and the barrier layer. The excess of the conductor film is removed from over the barrier layer, and the excess of the barrier layer overlying the patterned dielectric layer is removed, by a planarization process to form the planarized final copper structure. The planarized final copper structure comprising: the lower, recessed copper oxide-free initial copper structure; and an overlying planarized conductor film, wherein the overlying planarized conductor film isolates the lower, recessed copper oxide-free initial copper structure from the ambient atmosphere.

摘要翻译： 一种形成平面化最终铜结构的方法，包括以下步骤。 提供具有形成在其上的图案化电介质层的结构。 图案化的介电层具有形成在其中的开口。 在图案化的电介质层上形成阻挡层，衬在开口上。 初始的平坦化铜结构形成在阻挡层衬里的开口内，并且与阻挡层叠置在图案化的介电层上是平面的。 初始平坦化的铜结构在阻挡层的下方凹进在图案化的介电层上方一段距离以形成凹陷的铜结构。 形成在凹陷的铜结构上的任何氧化铜被去除。 在凹陷的无铜氧化物的初始铜结构和阻挡层上形成导体膜。 通过平坦化工艺去除覆盖在图案化电介质层上的阻挡层的过量，从而形成平坦化的最终铜结构。 平坦化的最终铜结构包括：较低的凹陷的无铜氧化物的初始铜结构; 和覆盖的平坦化导体膜，其中上覆的平坦化导体膜将较低的凹陷的无铜氧化物的初始铜结构与环境大气隔离。

公开(公告)号：US06211024B1

公开(公告)日：2001-04-03

申请号：US09495345

申请日：2000-02-01

申请人： Chi-Wen Liu ,  Kou-Yu Chou

发明人： Chi-Wen Liu ,  Kou-Yu Chou

IPC分类号： H01L21336

CPC分类号： H01L21/324 ,  H01L21/26513

摘要： A process for forming a shallow source/drain region, for a sub-micron MOSFET device, has been developed. The process features a process sequence comprised of a series of ion implantation procedures, followed by a low temperature, rapid thermal anneal procedure. Each ion implantation procedure, uses a specific energy and a specific dose, resulting in a series of ion implant regions, each located at a specific depth in the semiconductor substrate. A rapid thermal anneal is used to activate the implanted ions, forming the shallow source/drain region. The creation of several ion implant regions, reduced the risk of crystal damage which can result with the use of a single, more concentrated, ion implant region. The risk of crystal damage is also reduced via the use of a rapid thermal anneal procedure, which can be employed at lower temperatures than counterpart anneal procedures, that are used to distribute ions from a single, ion implanted region.

摘要翻译： 已经开发了用于形成用于亚微米MOSFET器件的浅源/漏区的工艺。 该方法具有由一系列离子注入程序组成的工艺顺序，随后是低温快速热退火程序。 每个离子注入程序使用比能量和特定剂量，产生一系列离子注入区域，每个离子注入区域位于半导体衬底中的特定深度处。 使用快速热退火来激活注入的离子，形成浅的源极/漏极区域。 创建几个离子植入区域，降低了使用单个更浓缩的离子注入区域导致的晶体损伤的风险。 通过使用快速热退火程序也可以降低晶体损坏的风险，该方法可以在比用于从单个离子注入区域分配离子的对应退火程序更低的温度下使用。

公开(公告)号：US09906634B2

公开(公告)日：2018-02-27

申请号：US15071122

申请日：2016-03-15

申请人： Chi Wen Liu ,  Ching Yu Chang ,  Kuo Ching Chiang

发明人： Chi Wen Liu ,  Ching Yu Chang ,  Kuo Ching Chiang

IPC分类号： H04M1/253 ,  H04W4/00 ,  H04L29/06 ,  H04M1/725 ,  H04W88/06 ,  H04W84/12 ,  G10L15/26

CPC分类号： H04M1/2535 ,  G10L13/00 ,  G10L15/26 ,  H04L29/06993 ,  H04L65/403 ,  H04M1/72502 ,  H04M1/72519 ,  H04M2250/02 ,  H04M2250/06 ,  H04W4/80 ,  H04W84/12 ,  H04W88/06

摘要： A portable device can transmit information through one of a mobile phone network and an Internet, wherein the portable device includes a text-based communication module to allow a user may synchronously transmit or receive data through a local area network, wherein the data is text, audio, video or the combination thereof. The text-based communication module of the portable device includes a text-to-speech recognition module used to convert a text data for outputting the text data by vocal, and a read determination module for determining read target terminals and unread target terminals when a user of the portable phone device activates the read determination module.

公开(公告)号：US20130270647A1

公开(公告)日：2013-10-17

申请号：US13448846

申请日：2012-04-17

申请人： Ming Zhu ,  Jin-Aun Ng ,  Chi-Wen Liu

发明人： Ming Zhu ,  Jin-Aun Ng ,  Chi-Wen Liu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/022 ,  H01L21/02337 ,  H01L21/02362 ,  H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a n-type filed effect transistor (nFET) formed on the semiconductor substrate and having a first gate stack including a high k dielectric layer, a capping layer on the high k dielectric layer, a p work function metal on the capping layer, and a polysilicon layer on the p work function metal; and a p-type filed effect transistor (pFET) formed on the semiconductor substrate and having a second gate stack including the high k dielectric layer, the p work function metal on the high k dielectric layer, and a metal material on the p work function metal.

公开(公告)号：US20130113073A1

公开(公告)日：2013-05-09

申请号：US13289666

申请日：2011-11-04

申请人： Chi-Wen Liu ,  Chao-Hsiung Wang

发明人： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L27/0629 ,  H01L23/5223 ,  H01L27/1203 ,  H01L27/1211 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.

摘要翻译： 集成电路可以包括与其它器件（例如finFET）同时形成的MOM电容器。 形成在基板上的电介质层具有第一半导体鳍片和第二半导体鳍片。 除去翅片的各顶部以形成电介质层中的相应凹部。 第一和第二电极形成在凹槽中。 第一和第二电极和中间介电层形成MOM电容器。

公开(公告)号：US08383938B2

公开(公告)日：2013-02-26

申请号：US12853276

申请日：2010-08-09

申请人： Chin-Lai Lin ,  Chih-Ming Fan ,  Chi-Wen Liu

发明人： Chin-Lai Lin ,  Chih-Ming Fan ,  Chi-Wen Liu

IPC分类号： H02G3/14

CPC分类号： G06F1/181

摘要： A sliding cover faceplate and an electronic device using the same are provided. The sliding cover faceplate includes a sliding cover, a cover plate, and a sliding structure. The cover plate is provided on the electronic device, and the sliding cover is disposed on one side of the cover plate. The sliding structure includes a guiding portion and an elastic positioning portion. The guiding portion is disposed on the cover plate and is connected to the sliding cover to guide the sliding cover to slide between a first location and a second location on the cover plate. The elastic positioning portion connects the cover plate with the sliding cover to provide an elastic force to the sliding cover, such that when the sliding cover slides close to the first location or the second location, the sliding cover is automatically positioned on the first location or the second location.

摘要翻译： 提供一种滑盖面板和使用其的电子装置。 滑盖面板包括滑盖，盖板和滑动结构。 盖板设置在电子设备上，滑盖位于盖板的一侧。 滑动结构包括引导部分和弹性定位部分。 引导部分设置在盖板上并连接到滑盖上，以引导滑盖在盖板上的第一位置和第二位置之间滑动。 弹性定位部分将盖板与滑动盖连接，以向滑动盖提供弹性力，使得当滑动盖滑动靠近第一位置或第二位置时，滑动盖自动定位在第一位置或 第二个位置。