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    Methods of fabricating integrated circuit gates by pretreating prior to oxidizing
    61.
    发明授权
    Methods of fabricating integrated circuit gates by pretreating prior to oxidizing 有权
    在氧化之前通过预处理制造集成电路门的方法

    公开(公告)号：US06864132B2

    公开(公告)日：2005-03-08

    申请号：US10373005

    申请日：2003-02-24

    Applicant: Jun-Kyu Cho ,  Si-Young Choi ,  Sun-Pil Youn ,  Sung-Man Kim ,  Ja-Hum Ku

    Inventor： Jun-Kyu Cho ,  Si-Young Choi ,  Sun-Pil Youn ,  Sung-Man Kim ,  Ja-Hum Ku

    IPC: H01L21/3213 ,  H01L21/28 ,  H01L29/51 ,  H01L21/8234

    CPC classification number: H01L29/518 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28247

    Abstract: Integrated circuit gates are fabricated by forming an insulated gate on an integrated circuit substrate, wherein the insulated gate includes a gate oxide on the integrated circuit substrate, a polysilicon pattern including polysilicon sidewalls, on the gate oxide, and a metal pattern on the polysilicon pattern. The insulated gate is pretreated with hydrogen and nitrogen gasses. The polysilicon sidewalls are then oxidized. The pretreating in hydrogen and nitrogen gasses prior to oxidizing can reduce growth in thickness of the gate oxide during the oxidizing and/or can reduce formation of whiskers on the metal pattern, compared to absence of the pretreatment.

    Abstract translation: 通过在集成电路基板上形成绝缘栅极来制造集成电路栅极，其中绝缘栅极包括在集成电路基板上的栅极氧化物，在栅极氧化物上包括多晶硅侧壁的多晶硅图案，以及多晶硅图案上的金属图案 。 绝缘栅极用氢气和氮气预处理。 然后将多晶硅侧壁氧化。 在氧化之前在氢气和氮气中预处理可以减少在氧化期间栅极氧化物的厚度增长和/或可以减少与不进行预处理相比在金属图案上形成晶须。

    Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer
    62.
    发明授权
    Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer 有权
    形成T型隔离层的方法，使用其形成升高的自对准硅源/漏区的方法，以及具有T形隔离层的半导体器件

    公开(公告)号：US06383877B1

    公开(公告)日：2002-05-07

    申请号：US09573268

    申请日：2000-05-18

    Applicant: Dong-ho Ahn ,  Ja-hum Ku ,  Chul-sung Kim ,  Jae-yoon Yoo ,  Sug-hun Hong ,  Chul-joon Choi

    Inventor： Dong-ho Ahn ,  Ja-hum Ku ,  Chul-sung Kim ,  Jae-yoon Yoo ,  Sug-hun Hong ,  Chul-joon Choi

    IPC: H01L21425

    CPC classification number: H01L29/66598 ,  H01L21/28518 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66636

    Abstract: A method of forming a T-shaped isolation layer, a method of forming an elevated salicide source/drain region using the same, and a semiconductor device having the T-shaped isolation layer are provided. In the method of forming the T-shaped isolation layer, an isolation layer having a narrow trench region in the lower portion thereof and a wide trench region in the upper portion thereof is formed on a semiconductor substrate. Also, in the method of forming the elevated salicide source/drain region, the method of forming the T-shaped isolation layer is used. In particular, conductive impurities can also be implanted into the lower portion of the wide trench region which constitutes the head of the T-shaped isolation layer and is extended to both sides from the upper end of the narrow trench region by controlling the depth of the wide trench region in an ion implantation step for forming the source/drain region.

    Abstract translation: 提供形成T形隔离层的方法，使用该方法形成提高的自对准硅化物源极/漏极区域的方法以及具有T形隔离层的半导体器件。 在形成T形隔离层的方法中，在半导体衬底上形成在其下部具有窄沟槽区和其上部宽沟槽区的隔离层。 此外，在形成升高的自对准硅化物源极/漏极区域的方法中，使用形成T形隔离层的方法。 特别地，也可以将导电杂质注入构成T形隔离层的头部的宽沟槽区域的下部，并且通过控制该窄沟槽区域的深度而从窄沟槽区域的上端延伸到两侧 在用于形成源极/漏极区域的离子注入步骤中形成宽沟槽区域。

    GATE OXIDE FILM INCLUDING A NITRIDE LAYER DEPOSITED THEREON AND METHOD OF FORMING THE GATE OXIDE FILM
    63.
    发明申请
    GATE OXIDE FILM INCLUDING A NITRIDE LAYER DEPOSITED THEREON AND METHOD OF FORMING THE GATE OXIDE FILM 审中-公开
    含氮绝缘膜的氮化物膜及其形成氧化膜的方法

    公开(公告)号：US20120241874A1

    公开(公告)日：2012-09-27

    申请号：US13071883

    申请日：2011-03-25

    Applicant: BYUNG-DONG KIM ,  Ja-Hum Ku

    Inventor： BYUNG-DONG KIM ,  Ja-Hum Ku

    IPC: H01L29/772 ,  H01L21/28

    CPC classification number: H01L21/28202 ,  H01L29/513 ,  H01L29/518

    Abstract: A method for forming a gate stack of a semiconductor device comprises depositing a gate oxide layer on a channel region of a semiconductor substrate using chemical vapor deposition, atomic layer deposition or molecular layer deposition, depositing a nitride layer on the gate oxide layer, oxidizing the deposited nitride layer, depositing a high-K dielectric layer on the oxidized nitride layer, and forming a metal gate on the high-K dielectric layer.

    Abstract translation: 一种用于形成半导体器件的栅极堆叠的方法包括：使用化学气相沉积，原子层沉积或分子层沉积在半导体衬底的沟道区上沉积栅极氧化物层，在栅极氧化物层上沉积氮化物层， 沉积的氮化物层，在氧化的氮化物层上沉积高K电介质层，并在高K电介质层上形成金属栅极。

    CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein
    66.
    发明授权
    CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein 有权
    CMOS集成电路器件在其中具有应力的NMOS和PMOS沟道区

    公开(公告)号：US07800134B2

    公开(公告)日：2010-09-21

    申请号：US12420936

    申请日：2009-04-09

    Applicant: Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

    Inventor： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

    IPC: H01L29/78

    CPC classification number: H01L21/823807 ,  H01L21/76816 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.

    Abstract translation: 形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。 覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第 具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。 然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。 此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

    Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby
    69.
    发明授权
    Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby 有权
    形成其中具有应力NMOS和PMOS沟道区的CMOS集成电路器件的方法及由此形成的电路

    公开(公告)号：US07534678B2

    公开(公告)日：2009-05-19

    申请号：US11691691

    申请日：2007-03-27

    Applicant: Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

    Inventor： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/76816 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.

    Abstract translation: 形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。 覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第 具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。 然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。 此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

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