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    Semiconductor memory with vertical memory transistors and method for fabricating it
    62.
    发明授权
    Semiconductor memory with vertical memory transistors and method for fabricating it 有权
    具有垂直存储晶体管的半导体存储器及其制造方法

    公开(公告)号：US07265413B2

    公开(公告)日：2007-09-04

    申请号：US11073205

    申请日：2005-03-05

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Thomas Schulz ,  Michael Specht

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Thomas Schulz ,  Michael Specht

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923 ,  H01L29/7926

    摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.

    摘要翻译： 本发明涉及具有多个存储单元的半导体存储器和用于形成存储单元的方法。 半导体存储器通常包括布置在衬底表面上的半导体层，其包括较深区域和较高区域之间的正常定位的台阶。 半导体存储器还包括掺杂接触区域，沟道区域，布置在栅极氧化物层上的俘获层和至少一个栅电极。 形成存储单元的方法包括图案化半导体层以形成较深的半导体区域和具有位于该区域之间的台阶的较高半导体区域。 该方法还包括形成第一氧化物层和俘获层，然后去除俘获层和第一氧化物层的部分，并且至少在掺杂区域，俘获层和台阶区域的区域上施加第二氧化物层， 以及向所述第二氧化物层施加栅电极，并且至少在所述较深半导体区域和所述较高半导体区域的区域中掺杂以形成更深的接触区域和更高的接触区域。

    Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement
    63.
    发明申请
    Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement 有权

    公开(公告)号：US20070158756A1

    公开(公告)日：2007-07-12

    申请号：US11649470

    申请日：2007-01-04

    申请人： Lars Dreeskornfeld ,  Franz Hofmann ,  Johannes Luyken ,  Michael Specht

    发明人： Lars Dreeskornfeld ,  Franz Hofmann ,  Johannes Luyken ,  Michael Specht

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823412 ,  H01L21/823437 ,  H01L29/66818 ,  H01L29/7851

    摘要： The present invention provides a production method for a FinFET transistor arrangement, and a corresponding FinFET transistor arrangement. The method comprises the following steps: provision of a substrate (106, 108); formation of an active region (1) on the substrate, said active region having a source region (114), a drain region (116) and an intervening fin-like channel region (113b′; 113b″) for each individual FinFET transistor; formation of a gate dielectric (11) and a gate region (13, 14, 15) over the fin-like channel region (113b′; 113b″) for each individual FinFET transistor; the formation of the fin-like channel region (113b′; 113b″) having the following steps: formation of a hard mask (S1-S4) on the active region (1), said hard mask having a pad oxide layer (30), an overlying pad nitride layer (50) and nitride sidewall spacers (7); anisotropic etching of the active layer (1) using the hard mask (S1-S4) for the formation of STI trenches (G1-G5); filling of the STI trenches (G1-G5) with an STI oxide filling (9); polishing-back of the STI oxide filling (9) as far as the top side of the hard mask (S1-S4); etching-back of the polished-back STI oxide filling (9) as far as a residual height (h′) in the STI trenches (G1-G5); selective removal of the pad nitride layer (50) and the nitride sidewall spacers (7) with respect to the pad oxide layer (30), the etched-back STI oxide filling (9) and the active region (1) for the formation of a modified hard mask (S1′-S4′); anisotropic etching of the active layer (1) using the modified hard mask (S1′-S4′) for the formation of widened STI trenches (G1′-G5′), the fin-like channel regions (113b′; 113b″) of the active region (1) remaining for each individual FinFET transistor.

    Semiconductor memory device
    65.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060267084A1

    公开(公告)日：2006-11-30

    申请号：US11139976

    申请日：2005-05-31

    申请人： Wolfgang Rosner ,  Franz Hofmann ,  Michael Specht ,  Martin Stadele ,  Johannes Luyken

    发明人： Wolfgang Rosner ,  Franz Hofmann ,  Michael Specht ,  Martin Stadele ,  Johannes Luyken

    IPC分类号： H01L29/76

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7393

    摘要： A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

    摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元具有相应的晶体管。 晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，其中所述漏极区域和源极区域嵌入在所述晶体管本体的第一表面上的晶体管本体中，栅极 具有栅极电介质层和栅电极的结构。 所述栅极结构布置在所述漏极区域和所述源极区域之间。 提供了所述第一导电类型的发射极区域，其中所述发射极区域布置在所述漏极区域的顶部。

    Semiconductor memory device
    66.
    发明申请
    Semiconductor memory device 审中-公开
    半导体存储器件

    公开(公告)号：US20060267064A1

    公开(公告)日：2006-11-30

    申请号：US11139977

    申请日：2005-05-31

    申请人： Wolfgang Rosner ,  Franz Hofmann ,  Michael Specht ,  Martin Stadele

    发明人： Wolfgang Rosner ,  Franz Hofmann ,  Michael Specht ,  Martin Stadele

    IPC分类号： H01L29/94

    CPC分类号： H01L27/10873 ,  H01L21/7624 ,  H01L27/10802 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/7841 ,  H01L29/945

    摘要： The semiconductor memory device comprises a plurality of memory cells. Each memory cell comprises a respective transistor and a respective capacitor unit. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, the drain area and source area are embedded in the transistor body on a first surface of the transistor body, and a gate structure having a gate dielectric layer and a gate electrode, the gate structure is arranged between the drain area and the source area. An isolation trench is arranged adjacent to said transistor body, having a dielectric layer and a conductive material, wherein the isolation trench is at least partially filled with the conductive material. The conductive material is isolated by said dielectric layer from the transistor body. The capacitor unit is formed by the transistor body representing a first electrode and the conductive material representing the second electrode.

    摘要翻译： 半导体存储器件包括多个存储单元。 每个存储单元包括相应的晶体管和相应的电容器单元。 晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，漏极区域和源极区域嵌入在晶体管本体的第一表面上，并且栅极 具有栅极介电层和栅电极的结构，栅极结构布置在漏极区域和源极区域之间。 绝缘沟槽被布置成与所述晶体管本体相邻，具有电介质层和导电材料，其中隔离沟槽至少部分地被导电材料填充。 导电材料通过所述介电层与晶体管本体隔离。 电容器单元由表示第一电极的晶体管体和表示第二电极的导电材料形成。

    Charge-trapping memory cell and method for production
    68.
    发明申请
    Charge-trapping memory cell and method for production 有权
    电荷俘获记忆体和生产方法

    公开(公告)号：US20060115978A1

    公开(公告)日：2006-06-01

    申请号：US11000350

    申请日：2004-11-30

    申请人： Michael Specht ,  Wolfgang Roesner ,  Franz Hofmann

    发明人： Michael Specht ,  Wolfgang Roesner ,  Franz Hofmann

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76895 ,  H01L21/28282 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/792

    摘要： The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer sequence is arranged on the fins. Wordlines are arranged across the fins, and source/drain regions are located in the fins between the wordlines and at the ends of the fins. There are preferably self-aligned contact areas of the source/drain regions at the ends of the fins, each contact area being common to the fins of one of said pairs. Select transistors and select lines are provided for the first and second fins individually to enable a separate addressing of the memory cells.

    摘要翻译： 存储单元阵列包括多个平行翅片，它们设置成彼此相距约40nm的位线，并且具有小于约30nm的横向尺寸，被细分成相邻的第一和第二鳍片对。 鳍片上布置有电荷俘获记忆层序列。 词汇排列在翅片之间，源极/漏极区域位于字线之间的翅片和翅片的末端。 优选地，在鳍片的端部处的源极/漏极区域的自对准接触区域，每个接触区域对于所述成对中的一个的翅片是共同的。 选择晶体管，并且单独地为第一和第二散热片提供选择线以使得能够单独寻址存储器单元。

    NROM semiconductor memory device and fabrication method
    69.
    发明申请
    NROM semiconductor memory device and fabrication method 失效
    NROM半导体存储器件及其制造方法

    公开(公告)号：US20060108646A1

    公开(公告)日：2006-05-25

    申请号：US11282904

    申请日：2005-11-18

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Michael Specht

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Michael Specht

    IPC分类号： H01L29/76 ,  H01L21/8234

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7923

    摘要： This invention relates to a method for producing an NROM semiconductor memory device and a corresponding NROM semiconductor memory device. The inventive production method comprises the following steps: a plurality of spaced-apart U-shaped MOSFETS are provided along rows in a first direction and along gaps in a second direction inside trenches of a semiconductor substrate, said U-shaped MOSFETS comprising a multilayer dielectric, especially an ONO dielectric, for trapping charges; source/drain areas are provided between the U-shaped MOSFETS in intermediate spaces located between the rows that extend parallel to the gaps; insulating trenches are provided in the source/drain areas between the U-shaped MOSFETS of adjacent gaps, down to a certain depth in the semiconductor substrate, said insulating trenches cutting up the source/drain areas into respective bit lines; the insulating trenches are filled with an insulating material; and word lines are provided for connecting respective rows of U-shaped MOSFETS.

    摘要翻译： 本发明涉及一种制造NROM半导体存储器件和相应的NROM半导体存储器件的方法。 本发明的制造方法包括以下步骤：在半导体衬底的沟槽内沿着第一方向并沿着第二方向的间隙沿着行设置多个间隔开的U形MOSFET，所述U形MOSFETS包括多层电介质 ，特别是用于捕获电荷的ONO电介质; 源极/漏极区域设置在位于平行于间隙延伸的行之间的中间空间中的U形MOSFET之间; 绝缘沟槽设置在相邻间隙的U形MOSFET之间的源极/漏极区域中，在半导体衬底内向下到达一定深度，所述绝缘沟槽将源极/漏极区域切割成相应的位线; 绝缘槽填充绝缘材料; 并且提供用于连接各行的U形MOSFET的字线。