公开(公告)号：US10305456B2

公开(公告)日：2019-05-28

申请号：US15605536

申请日：2017-05-25

Applicant: STMicroelectronics SA

Inventor： Hanae Zegmout ,  Denis Pache ,  Stephane Le Tual

IPC: H03K3/42 ,  H01S5/00 ,  H03M1/00

Abstract: The present disclosure relates to a device for converting an optical pulse to an electronic pulse includes a photoresistor having first and second terminals and being capable of receiving a pulsed laser signal arising from a mode-locked laser source The first terminal is linked to a node for applying a reference potential via a resistive element and a capacitive element connected in parallel. The second terminal is connected to a node for applying a supply potential.

公开(公告)号：US10263603B2

公开(公告)日：2019-04-16

申请号：US15462494

申请日：2017-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Pascal Urard ,  Alok Kumar Tripathi

IPC: H03K3/012 ,  H03K3/356 ,  H03K19/00 ,  H03K3/0233 ,  H03K3/3562

Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.

公开(公告)号：US10249427B2

公开(公告)日：2019-04-02

申请号：US15223148

申请日：2016-07-29

Applicant: STMICROELECTRONICS SA

Inventor： Vincent Knopik

IPC: H01Q1/24 ,  H01F27/28 ,  H01L23/522 ,  H03H7/42 ,  H01F27/29 ,  H01F38/14 ,  H01F41/04 ,  H01F41/10 ,  H01Q1/36 ,  H01Q1/48 ,  H01Q1/50 ,  H01Q7/00

Abstract: A transformer of the symmetric-asymmetric type includes comprising a primary inductive circuit and a secondary inductive circuit formed in a same plane by respective interleaved and stacked metal tracks. A first crossing region includes a pair of connection plates facing one another, with each connection plate having a rectangular shape that is wider than the metal tracks, and diagonally connected to tracks of the secondary inductive circuit.

公开(公告)号：US20190094462A1

公开(公告)日：2019-03-28

申请号：US16185654

申请日：2018-11-09

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Robert Manouvrier ,  Jean-Francois Carpentier ,  Patrick LeMaitre

IPC: G02B6/124 ,  G02F1/025 ,  G02B6/30

Abstract: An electro-optic device may include a photonic chip having an optical grating coupler at a surface. The optical grating coupler may include a first semiconductor layer having a first base and first fingers extending outwardly from the first base. The optical grating coupler may include a second semiconductor layer having a second base and second fingers extending outwardly from the second base and being interdigitated with the first fingers to define semiconductor junction areas, with the first and second fingers having a non-uniform width. The electro-optic device may include a circuit coupled to the optical grating coupler and configured to bias the semiconductor junction areas and change one or more optical characteristics of the optical grating coupler.

公开(公告)号：US10186022B2

公开(公告)日：2019-01-22

申请号：US15636294

申请日：2017-06-28

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Mahesh Chandra ,  Antoine Drouot

IPC: G06T5/20 ,  G06T11/60 ,  G06T5/00 ,  G06K9/46 ,  G06K9/56

Abstract: Various embodiments provide an optimized image filter. The optimized image and video obtains an input image and selects a target pixel for modification. Difference values are then determined between the selected target pixel and each reference pixel of a search area. Subsequently, a weighting function is used to determine weight values for each of the reference pixels of the search area based on their respective difference value. The selected target pixel is then modified by the optimized image filter using the determined weight values. A new target pixel in an apply patch is then selected for modification. The new target pixel is modified using the previously determined weight values reassigned to a new set of reference pixels. The previously determined weight values are reassigned to the new set of reference pixels based on each of the new set of reference pixels' position relative to the new target pixel.

公开(公告)号：US20190020467A1

公开(公告)日：2019-01-17

申请号：US16029457

申请日：2018-07-06

Applicant: STMICROELECTRONICS SA ,  STMicroelectronics Razvoj Polprevodnikov d.o.o.

Inventor： Maksimiljan STIGLIC ,  Nejc SUHADOLNIK ,  Marc HOUDEBINE

IPC: H04L7/033 ,  H04B5/00 ,  G06K19/07 ,  H03L7/099 ,  H03C3/09

Abstract: A transponder communicates with a reader using active load modulation. The transponder includes a digital phase locked loop (DPLL), which, in operation, generates an active load modulation (ALM) carrier clock synchronized to carrier clock of the reader. Between transmission of data frames, the DPLL is placed in a lock mode of operation in which a feedback loop of the DPLL is closed. Within a transmitted data frame having a duration, the DPLL is placed, for the duration of the transmitted data frame, in a hold mode of operation in which the feedback loop is opened. A phase of the ALM carrier clock is adjusted at least once during the duration of the transmitted data frame.

公开(公告)号：US20180331672A1

公开(公告)日：2018-11-15

申请号：US15978894

申请日：2018-05-14

Applicant: STMicroelectronics SA

Inventor： Renald Boulestin

IPC: H03H11/24 ,  H03F3/19 ,  H03G3/30 ,  H04B1/40

CPC classification number: H03H11/245 ,  H03F3/19 ,  H03F2200/451 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/008 ,  H03G3/3036 ,  H03G2201/307 ,  H03H7/24 ,  H04B1/40

Abstract: An embodiment attenuator includes a plurality of circuits coupled in series. A respective circuit includes a first capacitor connected between an input node of the respective circuit and an output node of the respective circuit, and a second capacitor connected between the output node of the respective circuit and a reference node. The output node of the respective circuit, other than a last circuit of the plurality of circuits, is connected to the input node of a successive circuit. The attenuator further includes a plurality of selectors, in which the respective circuit is associated with a respective selector that is coupled between the output node of the respective circuit and an output node of the attenuator.

公开(公告)号：US20180268522A1

公开(公告)日：2018-09-20

申请号：US15976677

申请日：2018-05-10

Applicant: STMicroelectronics SA ,  STMicroelectronics (Research & Development) Limited

Inventor： Ed Hawkins ,  Arnaud Bourge ,  Chandan Siyag

IPC: G06T3/40 ,  G06T7/50 ,  H01L31/02

CPC classification number: G06T3/4053 ,  G06T7/50 ,  H01L31/02027

Abstract: An electronic device includes a SPAD array and readout circuitry coupled thereto. The readout circuitry generates a depth map having a first resolution, and a signal count map having a second resolution greater than the first resolution. The depth map corresponds to distance observations to an object. The signal count map corresponds to intensity observation sets of the object, with each intensity observation set including intensity observations corresponding to a respective distance observation in the depth map. An upscaling processor is coupled to the readout circuitry to calculate upscaling factors for each intensity observation set so that each distance observation has respective upscaling factors associated therewith. The depth map is then upscaled from the first resolution to the second resolution based on the respective upscaling factors.

公开(公告)号：US10062681B2

公开(公告)日：2018-08-28

申请号：US15591565

申请日：2017-05-10

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  Centre National de la Recherche Scientifique

Inventor： Yohann Solaro ,  Sorin Cristoloveanu ,  Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/74 ,  H01L29/749 ,  H01L29/747 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L27/12

CPC classification number: H01L27/0262 ,  H01L27/1203 ,  H01L29/1012 ,  H01L29/42308 ,  H01L29/66477 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7833

Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.

公开(公告)号：US20180166318A1

公开(公告)日：2018-06-14

申请号：US15892696

申请日：2018-02-09

Applicant: STMicroelectronics SA

Inventor： Didier Dutartre ,  Herve Jaouen

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/763 ,  H01L29/04

Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.