公开(公告)号：US20130321961A1

公开(公告)日：2013-12-05

申请号：US13482413

申请日：2012-05-29

申请人： Ying-Chang Lin ,  Da-Wei Lai

发明人： Ying-Chang Lin ,  Da-Wei Lai

IPC分类号： H02H9/04 ,  H05K13/00

CPC分类号： H02H9/046 ,  H01L2924/0002 ,  Y10T29/49117 ,  H01L2924/00

摘要： A ESD protection scheme is disclosed for circuits with multiple power domains. Embodiments include: coupling a first power clamp to a first power rail and a first ground rail of a first domain; coupling a second power clamp to a second power rail and a second ground rail of a second domain; providing a blocking circuit for blocking current from an ESD event; providing an I/O interface connection in the first domain for transmitting signals from the first domain to the blocking circuit; providing a core interface connection in the second domain for transmitting signals from the blocking circuit to the second domain; coupling an input connection of the blocking circuit to the I/O interface connection; and coupling an output connection of the blocking circuit to a core interface connection.

摘要翻译： 公开了具有多个电源域的电路的ESD保护方案。 实施例包括：将第一电源钳连接到第一电源轨和第一磁畴的第一接地轨; 将第二电力钳耦合到第二电力轨道和第二区域的第二接地轨道; 提供阻塞来自ESD事件的电流的阻塞电路; 在第一域中提供I / O接口连接，用于将信号从第一域传输到阻塞电路; 在第二域中提供核心接口连接，用于将信号从阻塞电路传输到第二域; 将阻塞电路的输入连接耦合到I / O接口连接; 并将阻塞电路的输出连接耦合到核心接口连接。

公开(公告)号：US20130320398A1

公开(公告)日：2013-12-05

申请号：US13483322

申请日：2012-05-30

申请人： Da-Wei Lai

发明人： Da-Wei Lai

IPC分类号： H01L21/332 ,  H01L29/74

CPC分类号： H01L29/744 ,  H01L27/0262 ,  H01L27/0641 ,  H01L28/20 ,  H01L28/40 ,  H01L29/1012 ,  H01L29/7436

摘要： An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad.

公开(公告)号：US20130222952A1

公开(公告)日：2013-08-29

申请号：US13406537

申请日：2012-02-28

申请人： Da-Wei LAI ,  Mahadeva Iyer NATARAJAN ,  Manjunatha Govinda PRABHU ,  Ryan SHAN

发明人： Da-Wei LAI ,  Mahadeva Iyer NATARAJAN ,  Manjunatha Govinda PRABHU ,  Ryan SHAN

IPC分类号： H02H9/04 ,  H01R43/00

CPC分类号： H02H9/046 ,  Y10T29/49117

摘要： A device having an ESD module is disclosed. The ESD module includes an ESD circuit coupled between first and second rails and a control circuit coupled between the rails and to the ESD circuit. When the control circuit senses an ESD event, it causes the ESD circuit to create a current path between the rails to dissipate ESD current. When no ESD event is sensed, the control circuit ensures that no current path is created between the rails to prevent latch-up.

摘要翻译： 公开了具有ESD模块的装置。 ESD模块包括耦合在第一和第二导轨之间的ESD电路和耦合在轨道和ESD电路之间的控制电路。 当控制电路感测到ESD事件时，会使ESD电路在轨道之间产生电流路径，以消耗ESD电流。 当没有感测到ESD事件时，控制电路确保在轨道之间不产生电流路径以防止闩锁。

公开(公告)号：US20130222950A1

公开(公告)日：2013-08-29

申请号：US13406534

申请日：2012-02-28

申请人： Da-Wei LAI ,  Mahadeva Iyer NATARAJAN

发明人： Da-Wei LAI ,  Mahadeva Iyer NATARAJAN

IPC分类号： H02H7/00 ,  H01L21/8234 ,  H01L21/761

CPC分类号： H03K17/082 ,  H01L23/62 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device is presented. The device includes a first circuit coupled to first and second power rails of the device. The first circuit is subject to a latch up event in the presence of a latch up condition. The latch up event includes a low resistance path created between the first and second power rails. The device also includes a latch up sensing (LUS) circuit coupled to the first circuit. The LUS circuit is configured to receive a LUS input signal from the first circuit and generates a LUS output signal to the first circuit. When the input signal is an active latch up signal which indicates the presence of a latch up condition, the LUS circuit generates an active LUS output signal which creates a break in the low resistance path to terminate the latch up event.

摘要翻译： 提供了一个设备。 该装置包括耦合到该装置的第一和第二电力轨的第一电路。 在存在闩锁状态的情况下，第一电路经历闩锁事件。 闩锁事件包括在第一和第二电源轨之间产生的低电阻路径。 该装置还包括耦合到第一电路的闭锁检测（LUS）电路。 LUS电路被配置为从第一电路接收LUS输入信号并且产生到第一电路的LUS输出信号。 当输入信号是指示存在锁存状态的有效锁存信号时，LUS电路产生有效的LUS输出信号，该信号在低电阻路径中产生中断以终止锁存事件。

公开(公告)号：US20130163129A1

公开(公告)日：2013-06-27

申请号：US13770544

申请日：2013-02-19

申请人： Da-Wei LAI ,  Wade MA

发明人： Da-Wei LAI ,  Wade MA

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) protection circuit includes a clamp transistor, and inverter, a resistance-capacitance (RC) circuit, and a current mirror. The clamp transistor is coupled between a first supply node and a second supply node. The inverter has an input end and an output end, and the output end of the inverter is coupled with a gate of the clamp transistor. The RC circuit is coupled to the first supply node. The current mirror includes a first transistor and a second transistor. The first transistor is coupled between the input end of the inverter and the second supply node, and the second transistor is coupled between the RC circuit and the second supply node.

摘要翻译： 静电放电（ESD）保护电路包括钳位晶体管，反相器，电阻电容（RC）电路和电流镜。 钳位晶体管耦合在第一电源节点和第二电源节点之间。 逆变器具有输入端和输出端，反相器的输出端与钳位晶体管的栅极耦合。 RC电路耦合到第一电源节点。 电流镜包括第一晶体管和第二晶体管。 第一晶体管耦合在反相器的输入端和第二电源节点之间，第二晶体管耦合在RC电路和第二电源节点之间。

公开(公告)号：US20130127059A1

公开(公告)日：2013-05-23

申请号：US13299100

申请日：2011-11-17

申请人： Chih-Wei Lai ,  Ming-Che Ho ,  Tzong-Hann Yang ,  Chien Rhone Wang ,  Chia-Tung Chang ,  Hung-Jui Kuo ,  Chung-Shi Liu

发明人： Chih-Wei Lai ,  Ming-Che Ho ,  Tzong-Hann Yang ,  Chien Rhone Wang ,  Chia-Tung Chang ,  Hung-Jui Kuo ,  Chung-Shi Liu

IPC分类号： H01L23/48 ,  H01L21/66 ,  G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5072 ,  H01L23/488 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

摘要： A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

公开(公告)号：US08441314B1

公开(公告)日：2013-05-14

申请号：US13558904

申请日：2012-07-26

申请人： Gregory Starr ,  Kang Wei Lai ,  Richard Y. Chang

发明人： Gregory Starr ,  Kang Wei Lai ,  Richard Y. Chang

IPC分类号： H01L25/00

CPC分类号： H03K19/017581 ,  G06F1/10

摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

摘要翻译： 在具有高速串行接口通道的可编程逻辑器件中，用于向这些高速串行接口的动态相位对准电路提供一个或多个高速时钟的时钟分配网络包括至少一个可分段的总线（例如使用可调 缓冲区）。 这允许总线在高速串行接口以不同的速度运行时被分成不同的部分，可以连接到不同的时钟源。 在一个实施例中，分段元件（例如，上述缓冲器）位于所选择的通道（例如，每第四通道）之间，限制不同段的大小。 在另一个实施例中，分段元件位于每个通道之间，允许完全用户在选择段的大小时的自由度。 因此，代替为每个时钟源提供总线，通过分割单个总线，可以使多个时钟可用于不同的通道。

公开(公告)号：US20130098675A1

公开(公告)日：2013-04-25

申请号：US13279132

申请日：2011-10-21

申请人： Jan Bos ,  David Heald ,  Yen Hua Lin ,  Yung-Wei Lai ,  Jui-Chih Liao ,  Yoke-Hou Tan ,  Nageswara Tadepalli ,  Yan Du ,  Jianwei Liu ,  Richard Pietri

发明人： Jan Bos ,  David Heald ,  Yen Hua Lin ,  Yung-Wei Lai ,  Jui-Chih Liao ,  Yoke-Hou Tan ,  Nageswara Tadepalli ,  Yan Du ,  Jianwei Liu ,  Richard Pietri

IPC分类号： H05K7/00 ,  B05D5/12

CPC分类号： G02B26/001 ,  B81B3/0005 ,  B81C1/00285 ,  B81C2201/112

摘要： This disclosure provides apparatus, systems and methods for manufacturing electromechanical systems (EMS) packages. One method includes making an EMS package that includes an out-gassable anti-stiction coating. The anti-stiction coating may be a solvent that is included within part of a desiccant mixture. In some implementations, the method includes sealing an EMS device into a package and then heating the package using a temperature profile that out-gasses at least a portion of a residual solvent. The method may include an incubation bake cycle to distribute anti stiction material to display elements within the EMS package. The incubation bake cycle may also more evenly distribute contaminants within the EMS package so as to reduce their effects.

摘要翻译： 本公开提供了用于制造机电系统（EMS）封装的装置，系统和方法。 一种方法包括制造包含无气体防粘涂层的EMS包装。 抗静电涂层可以是包含在干燥剂混合物的一部分内的溶剂。 在一些实施方式中，该方法包括将EMS装置密封到包装中，然后使用排出至少一部分残留溶剂的温度分布来加热包装。 该方法可以包括孵育烘烤循环，以将抗静电材料分配到EMS包装内的显示元件。 温育烘烤循环还可以更均匀地分布EMS包装内的污染物，以减少其影响。

公开(公告)号：US20130023065A1

公开(公告)日：2013-01-24

申请号：US13189287

申请日：2011-07-22

申请人： Chien Rhone Wang ,  Tzu-Cheng Lin ,  Yu-Jen Cheng ,  Chih-Wei Lai ,  Hung-Pin Chang ,  Tsang-Jiuh Wu

发明人： Chien Rhone Wang ,  Tzu-Cheng Lin ,  Yu-Jen Cheng ,  Chih-Wei Lai ,  Hung-Pin Chang ,  Tsang-Jiuh Wu

IPC分类号： H01L21/66

CPC分类号： H01J37/32963

摘要： Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.

摘要翻译： 执行终点确定的方法和装置。 一种方法包括将晶片接收到用于进行RIE蚀刻的蚀刻工具室中; 开始RIE蚀刻以在晶片中形成通孔; 接收与RIE蚀刻工艺相关的蚀刻工具室的一个或多个物理参数的原位测量; 为腔室中的RIE蚀刻提供虚拟计量模型; 将接收到的原位测量值输入到腔室中的RIE蚀刻的虚拟测量模型; 执行虚拟计量模型以通过深度估计电流; 将经过深度的估计电流与目标深度进行比较; 并且当比较指示当前经过深度在目标深度的预定阈值内时; 输出停止信号。 公开了一种用于该方法实施例的装置。

公开(公告)号：US20120128092A1

公开(公告)日：2012-05-24

申请号：US13159385

申请日：2011-06-13

申请人： Jie-Wei Lai ,  Yang-Chuan Chen

发明人： Jie-Wei Lai ,  Yang-Chuan Chen

IPC分类号： H04L27/00

CPC分类号： H04L27/0008 ,  H04L27/12 ,  H04L27/3427

摘要： A digital signal processing circuit includes a combining stage and an output stage. The combining stage is arranged to receive a plurality of non-overlapping clock signals having a same frequency but different phases, receive a plurality of first input bit streams, and generate a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals. The output stage is arranged to generate an output according to the first output bit stream. A digital signal processing method includes: receiving a plurality of non-overlapping clock signals having a same frequency but different phases; receiving a plurality of first input bit streams; generating a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals; and generating an output according to the first output bit stream.

摘要翻译： 数字信号处理电路包括组合级和输出级。 组合级被布置为接收具有相同频率但不同相位的多个不重叠的时钟信号，接收多个第一输入比特流，并且通过根据非接收方式组合第一输入比特流来生成第一输出比特流， - 重叠的时钟信号。 输出级被布置成根据第一输出位流产生输出。 数字信号处理方法包括：接收具有相同频率但不同相位的多个非重叠时钟信号; 接收多个第一输入比特流; 通过根据所述非重叠时钟信号组合所述第一输入比特流来产生第一输出比特流; 以及根据第一输出比特流生成输出。