公开(公告)号：US20090117695A1

公开(公告)日：2009-05-07

申请号：US12260674

申请日：2008-10-29

Applicant: Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L21/8249

CPC classification number: H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

Abstract: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

Abstract translation: 提供了通过机械单轴应变增强性能的BiCMOS器件。 本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。 具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。 除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。

公开(公告)号：US20090075442A1

公开(公告)日：2009-03-19

申请号：US11855701

申请日：2007-09-14

Applicant: Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ho ,  Wen-Chin Lee

Inventor： Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ho ,  Wen-Chin Lee

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/665 ,  H01L29/7847

Abstract: A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method provides for a substrate, which includes a source/drain for an NMOS transistor, and a PMOS transistor. A first barrier layer is formed on the substrate and a first stressor material is formed on the first barrier layer. The first barrier layer is selectively removed from the PMOS transistor. The substrate is flash annealed and the remaining first stressor material and barrier layer is removed from the substrate.

Abstract translation: 公开了用于制造拉伸应变NMOS和压缩应变PMOS晶体管对的半导体器件和方法，其中应力源材料是牺牲的。 该方法提供了一种衬底，其包括用于NMOS晶体管的源极/漏极和PMOS晶体管。 在基板上形成第一阻挡层，在第一阻挡层上形成第一应力源材料。 从PMOS晶体管选择性地去除第一势垒层。 衬底被闪光退火，剩余的第一应力材料和阻挡层从衬底上去除。

公开(公告)号：US20080242071A1

公开(公告)日：2008-10-02

申请号：US11745862

申请日：2007-05-08

Applicant: Ching-Ya Wang ,  Wen-Chin Lee ,  Denny Tang

Inventor： Ching-Ya Wang ,  Wen-Chin Lee ,  Denny Tang

IPC: H01L21/3205

CPC classification number: H01L21/28185 ,  H01L21/2822 ,  H01L29/51

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer over the treated dielectric layer, and patterning and etching the dielectric layer and conductive layer to form a gate structure. The carbon containing group includes an OCH3 or CN species.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供半导体衬底，在半导体衬底上形成电介质层，用含碳基团处理电介质层，在经处理的电介质层上形成导电层，以及图案化和蚀刻电介质层和导电层以形成 门结构。 含碳基团包括OCH 3或CN物质。

公开(公告)号：US20080145982A1

公开(公告)日：2008-06-19

申请号：US12036616

申请日：2008-02-25

Applicant: Chih-Hsin KO ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

Inventor： Chih-Hsin KO ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

IPC: H01L21/00 ,  H01L21/3205

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/78618 ,  Y10S257/90

Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

公开(公告)号：US07369118B2

公开(公告)日：2008-05-06

申请号：US10996459

申请日：2004-11-26

Applicant: Wen-Chin Lee ,  Hsiang-Kuang Chen

Inventor： Wen-Chin Lee ,  Hsiang-Kuang Chen

IPC: G09G5/08

CPC classification number: G06F3/0362 ,  G06F3/0383

Abstract: A magnetic oscillation metric controller applied to computer peripheral or electronic communication system essentially operating on a scrolling wheel for lateral metric control to provide precise, consistent, reliable and programmable adjustment oscillation sensitivity by driving a permanent magnet to generate signals of changed magnetic fields resulted from displacement; and retrieving the data of changed signals for achieving metric control purpose.

Abstract translation: 应用于计算机外围或电子通信系统的磁振荡度量控制器，其基本上在用于横向度量控制的滚动轮上操作，以通过驱动永久磁体以产生由位移产生的变化的磁场的信号来提供精确，一致，可靠和可编程的调节振荡灵敏度 ; 以及检索改变信号的数据以达到度量控制目的。

公开(公告)号：US20070269588A1

公开(公告)日：2007-11-22

申请号：US11309852

申请日：2006-10-13

Applicant: Wen-Chin Lee ,  Cheng-Hsien Lin

Inventor： Wen-Chin Lee ,  Cheng-Hsien Lin

IPC: C23C18/31

CPC classification number: H05K3/0035 ,  H05K3/0038 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/0554 ,  H05K2203/108

Abstract: A method for forming stacked via-holes on a printed circuit board includes the steps of: providing a printed circuit board having a conductive trace formed on a side surface thereof; forming a first copper-clad laminate on the side surface having the conductive trace; forming a number of first copper micro-via in a copper layer of the first copper-clad laminate; forming a second copper-clad laminate on the surface of the copper layer having the first copper micro-via of the first copper-clad laminate; forming a number of second copper micro-via in a copper layer of the second copper-clad laminate by a first laser on the basis of the first copper micro-via, each second copper micro-via being located corresponding to its correspondingly first copper micro-via; and removing corresponding resin layer portions of the first and second copper-clad laminates, using a second laser, to yield the respective stacked via-holes.

Abstract translation: 一种在印刷电路板上形成堆叠的通孔的方法包括以下步骤：提供在其侧表面上形成有导电迹线的印刷电路板; 在具有导电迹线的侧表面上形成第一覆铜层压板; 在第一覆铜层压板的铜层中形成多个第一铜微通孔; 在具有第一覆铜层压板的第一铜微通孔的铜层的表面上形成第二覆铜层压板; 基于第一铜微通孔，通过第一激光在第二覆铜层压板的铜层中形成多个第二铜微通孔，每个第二铜微通孔对应于其相应的第一铜微通孔 -通过; 并使用第二激光器除去第一和第二覆铜层压板的相应树脂层部分，以产生相应的堆叠通孔。

公开(公告)号：US07183593B2

公开(公告)日：2007-02-27

申请号：US10745831

申请日：2003-12-24

Applicant: Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ge ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ge ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L29/86 ,  H01L29/205

CPC classification number: H01L27/0629 ,  H01L29/165 ,  H01L29/8605

Abstract: A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.

Abstract translation: 异质结构电阻器包括形成在半导体衬底的一部分中的掺杂区域，该衬底包括具有第一自然晶格常数的第一半导体材料。 掺杂区域包括覆盖半导体衬底的半导体层。 半导体层包括具有第二自然晶格常数的第二半导体材料。

公开(公告)号：US07176537B2

公开(公告)日：2007-02-13

申请号：US11134897

申请日：2005-05-23

Applicant: Wen-Chin Lee ,  Chung-Hu Ke ,  Min-Hwa Chi

Inventor： Wen-Chin Lee ,  Chung-Hu Ke ,  Min-Hwa Chi

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7839 ,  H01L21/26506 ,  H01L21/28097 ,  H01L21/32155 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66643

Abstract: A semiconductor device having a metal/metal silicide gate and a Schottky source/drain and a method of forming the same are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a metal or metal silicide gate electrode having a work function of less than about 4.3 eV or greater than about 4.9 eV overlying the gate dielectric, a spacer having a thickness of less than about 100 Å on a side of the gate electrode, and a Schottky source/drain having a work function of less than about 4.3 eV or greater than about 4.9 eV wherein the Schottky source/drain region overlaps the gate electrode. The Schottky source/drain region preferably has a thickness of less than about 300 Å.

Abstract translation: 提供了具有金属/金属硅化物栅极和肖特基源极/漏极的半导体器件及其形成方法。 半导体器件包括覆盖半导体衬底的栅极电介质，金属或金属硅化物栅电极，其功函数小于约4.3eV或大于约4.9eV，覆盖在栅极电介质上，具有小于约100的厚度的间隔物 并且肖特基源/漏极具有小于约4.3eV或大于约4.9eV的功函数，其中肖特基源极/漏极区与栅电极重叠。 肖特基源极/漏极区优选具有小于约的厚度。

公开(公告)号：US07112848B2

公开(公告)日：2006-09-26

申请号：US10939923

申请日：2004-09-13

Applicant: Wen-Chin Lee

Inventor： Wen-Chin Lee

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L29/7842 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78639

Abstract: Methods of manufacturing microelectronic device including, in one embodiment, forming a gate electrode over a substrate having an insulating layer interposing a bulk semiconductor portion and a thin semiconductor layer, and removing at least a portion of the thin semiconductor and insulating layers, thereby defining a pedestal comprising a portion of the thin semiconductor and insulating layers. Source/drain stressors are then formed contacting the source/drain extensions on opposing sides of the pedestal and substantially spanning a height no less than the pedestal.

公开(公告)号：US20060202254A1

公开(公告)日：2006-09-14

申请号：US11077479

申请日：2005-03-10

Applicant: Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

Inventor： Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  H01L29/66825 ,  H01L29/7391 ,  H01L29/8616

Abstract: A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.