公开(公告)号：US09916980B1

公开(公告)日：2018-03-13

申请号：US15380895

申请日：2016-12-15

Applicant: ASM IP Holding B.V.

Inventor： Werner Knaepen ,  Jan Willem Maes ,  Bert Jongbloed ,  Krzysztof Kamil Kachel ,  Dieter Pierreux ,  David Kurt De Roest

IPC: H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  C23C16/045 ,  C23C16/45525

Abstract: A method of forming a layer on a substrate is provided by providing the substrate with a hardmask material. The hardmask material is infiltrated with infiltration material during N infiltration cycles by: a) providing a first precursor to the hardmask material on the substrate in the reaction chamber for a first period T1; b) removing a portion of the first precursor for a second period T2; and, c) providing a second precursor to the hardmask material on the substrate for a third period T3, allowing the first and second precursor to react with each other forming the infiltration material.

公开(公告)号：US20170213732A1

公开(公告)日：2017-07-27

申请号：US15413848

申请日：2017-01-24

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Werner Knaepen ,  Bert Jongbloed

IPC: H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/02183 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31144

Abstract: An etch stop layer comprises a metal oxide comprising a metal selected from the group consisting of metals of Group 4 of the periodic table, metals of Group 5 of the periodic table, metals of Group 6 of the periodic table, and yttrium. The metal oxide forms exceptionally thin layers that are resiatant to ashing and HF exposure. Subjecting the etch stop layer to both ashing and HF etch processes removes less than 0.3 nm of the thickness of the etch stop layer, and more preferably less than 0.25 nm. The etch stop layer may be thin and may have a thickness of about 0.5-2 nm. In some embodiments, the etch stop layer comprises tantalum oxide (TaO).

公开(公告)号：US09711351B2

公开(公告)日：2017-07-18

申请号：US14830455

申请日：2015-08-19

Applicant: ASM IP Holding B.V.

Inventor： Bert Jongbloed ,  Dieter Pierreux

IPC: H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/02337 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3105

Abstract: In some embodiments, a nitride film is provided over a semiconductor substrate and densified. The nitride film may be a flowable nitride, which may be deposited to at least partially fill openings in the substrate. Densifying the film is accomplished without exposing the nitride film to plasma by exposing the nitride film to a non-plasma densifying agent in the process chamber. The non-plasma densifying agent may be a nitriding gas, a hydrogen scavenging gas, a silicon precursor, or a combination thereof.

公开(公告)号：US09576790B2

公开(公告)日：2017-02-21

申请号：US14686595

申请日：2015-04-14

Applicant: ASM IP HOLDING B.V.

Inventor： Viljami J. Pore ,  Yosuke Kimura ,  Kunitoshi Namba ,  Wataru Adachi ,  Hideaki Fukuda ,  Werner Knaepen ,  Dieter Pierreux ,  Bert Jongbloed

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/30 ,  C23C16/32 ,  C23C16/455 ,  H01L21/311

CPC classification number: H01L21/02112 ,  C23C16/045 ,  C23C16/30 ,  C23C16/32 ,  C23C16/45523 ,  C23C16/45525 ,  C23C16/45531 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/2254 ,  H01L21/31111

Abstract: Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B, C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. One or more of the boron and carbon containing films can have a thickness of less than about 30 angstroms. Methods of doping a semiconductor substrate are provided. Doping a semiconductor substrate can include depositing a boron and carbon film over the semiconductor substrate by exposing the substrate to a vapor phase boron precursor at a process temperature of about 300° C. to about 450° C., where the boron precursor includes boron, carbon and hydrogen, and annealing the boron and carbon film at a temperature of about 800° C. to about 1200° C.

Abstract translation: 提供了沉积硼和碳的膜的方法。 在一些实施例中，提供了沉积具有所需性质（诸如保形性和蚀刻速率）的B，C膜的方法。 一种或多种含硼和/或碳的前体可以在低于约400℃的温度下在基材上分解。含硼和碳的一种或多种膜可以具有小于约30埃的厚度。 提供掺杂半导体衬底的方法。 掺杂半导体衬底可以包括通过在大约300℃至大约450℃的工艺温度下将衬底暴露于气相硼前体而在半导体衬底上沉积硼和碳膜，其中硼前体包括硼， 碳和氢，并在约800℃至约1200℃的温度下退火硼和碳膜。

公开(公告)号：US20170011910A1

公开(公告)日：2017-01-12

申请号：US15240141

申请日：2016-08-18

Applicant: ASM IP Holding B.V.

Inventor： Bert Jongbloed ,  Dieter Pierreux ,  Cornelius A. van der Jeugd ,  Herbert Terhorst ,  Lucian Jdira ,  Radko G. Bankras ,  Theodorus G.M. Oosterlaken

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/56

CPC classification number: H01L21/02337 ,  C23C16/402 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02274

Abstract: In some embodiments, a reactive curing process may be performed by exposing a semiconductor substrate in a process chamber to an ambient containing hydrogen peroxide, with the pressure in the process chamber at about 300 Torr or less. In some embodiments, the residence time of hydrogen peroxide molecules in the process chamber is about five minutes or less. The curing process temperature may be set at about 500° C. or less. The curing process may be applied to cure flowable dielectric materials and may provide highly uniform curing results, such as across a batch of semiconductor substrates cured in a batch process chamber.

Abstract translation: 在一些实施方案中，反应性固化方法可以通过将处理室中的半导体衬底暴露于含有过氧化氢的环境中，其中处理室中的压力为约300托或更小。 在一些实施方案中，过氧化氢分子在处理室中的停留时间为约5分钟或更短。 固化过程温度可以设定在约500℃或更低。 固化过程可用于固化可流动介电材料，并且可以提供高度均匀的固化结果，例如在批处理室中固化的一批半导体衬底。

公开(公告)号：US20250079159A1

公开(公告)日：2025-03-06

申请号：US18815701

申请日：2024-08-26

Applicant: ASM IP Holding, B.V.

Inventor： Dieter Pierreux ,  Steven Van Aerde ,  Kelly Houben ,  Bert Jongbloed

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/455

Abstract: The technology of the present disclosure generally relates to the field of semiconductor devices. More particularly, semiconductor structures, systems, and methods for producing the same, comprising surface-modified silicon layers formed by reacting a deposited silicon layer with a halide reactant. The system comprising one or more reaction chamber constructed and arranged to hold a substrate; a silicon precursor vessel constructed and arranged to contain and evaporate a silicon precursor; a halide reactant vessel constructed and arranged to contain and evaporate a halide reactant; an exhaust source; and a controller; wherein the controller is configured to control the flow of said silicon precursor and said halide reactant into said reaction chamber, thereby forming a surface-modified silicon layer on said substrate.

公开(公告)号：US20250059644A1

公开(公告)日：2025-02-20

申请号：US18806814

申请日：2024-08-16

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux

IPC: C23C16/448 ,  C23C16/34 ,  C23C16/46 ,  H01L21/02

Abstract: A semiconductor processing system and method for depositing silicon layers on a plurality of substrates and a semiconductor precursor storage vessel is disclosed. The system may have a reaction chamber constructed and arranged to receive a boat with a plurality of substrates, a heater configured to heat the reaction chamber to a process temperature, and a silicon precursor source constructed and arranged to provide to the reaction chamber a halosilane.

公开(公告)号：US20240339359A1

公开(公告)日：2024-10-10

申请号：US18626758

申请日：2024-04-04

Applicant: ASM IP Holding B.V.

Inventor： René Henricus Jozef Vervuurt ,  Timothee Blanquart ,  Jihee Jeon ,  YongMin Yoo ,  Andrey Sokolov ,  Maarten Stokhof ,  Steven Van Aerde ,  Dieter Pierreux ,  Hussein Mehdi

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76879 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/02274

Abstract: The present disclosure relates to method and apparatuses for filling a gap on a substrate. The method comprises providing a substrate, which comprises at least one gap into a reaction chamber, depositing a silicon containing first layer onto the substrate; subjecting the first layer to a phosphorous containing compound to form a flowable intermediate material, which at least partially fills the at least one gap on the substrate; and forming a solid material comprising silicon.

公开(公告)号：US12000042B2

公开(公告)日：2024-06-04

申请号：US17885810

申请日：2022-08-11

Applicant: ASM IP Holding B.V.

Inventor： Jan Willem Maes ,  Werner Knaepen ,  Krzysztof Kamil Kachel ,  David Kurt De Roest ,  Bert Jongbloed ,  Dieter Pierreux

IPC: C23C16/455 ,  C23C16/04 ,  C23C16/26 ,  C23C16/44 ,  C23C16/448 ,  C23C16/52 ,  C23C16/56 ,  H01L21/033

CPC classification number: C23C16/45523 ,  C23C16/04 ,  C23C16/042 ,  C23C16/045 ,  C23C16/26 ,  C23C16/4412 ,  C23C16/448 ,  C23C16/4485 ,  C23C16/45527 ,  C23C16/52 ,  C23C16/56 ,  H01L21/0332 ,  H01L21/0337

Abstract: A sequential infiltration synthesis apparatus comprising:



a reaction chamber constructed and arranged to hold at least a first substrate;
a precursor distribution and removal system to provide to and remove from the reaction chamber a vaporized first or second precursor; and,
a sequence controller operably connected to the precursor distribution and removal system and comprising a memory provided with a program to execute infiltration of an infiltrateable material provided on the substrate when run on the sequence controller by:
activating the precursor distribution and removal system to provide and maintain the first precursor for a first period T1 in the reaction chamber;
activating the precursor distribution and removal system to remove a portion of the first precursor from the reaction chamber for a second period T2; and,
activating the precursor distribution and removal system to provide and maintain the second precursor for a third period T3 in the reaction chamber. The program in the memory is programmed with the first period T1 longer than the second period T2.

公开(公告)号：US20240150892A1

公开(公告)日：2024-05-09

申请号：US18404983

申请日：2024-01-05

Applicant: ASM IP Holding B.V.

Inventor： Pia Homm Jara ,  Werner Knaepen ,  Dieter Pierreux ,  Bert Jongbloed ,  Panagiota Arnou ,  Ren-Jie Chang ,  Qi Xie ,  Giuseppe Alessio Verni ,  Gido van der Star

IPC: C23C16/34 ,  C23C16/04 ,  C23C16/44 ,  C23C16/455 ,  C23C16/56 ,  H01L21/285

CPC classification number: C23C16/34 ,  C23C16/04 ,  C23C16/4408 ,  C23C16/45527 ,  C23C16/45544 ,  C23C16/56 ,  H01L21/28568

Abstract: The current disclosure relates to methods of forming a vanadium nitride-containing layer. The method comprises providing a substrate within a reaction chamber of a reactor and depositing a vanadium nitride-containing layer onto a surface of the substrate, wherein the deposition process comprises providing a vanadium precursor to the reaction chamber and providing a nitrogen precursor to the reaction chamber. The disclosure further relates to structures and devices comprising the vanadium nitride-containing layer.