公开(公告)号：US20240392435A1

公开(公告)日：2024-11-28

申请号：US18790702

申请日：2024-07-31

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Theodorus G.M. Oosterlaken ,  Herbert Terhorst ,  Lucian Jdira ,  Bert Jongbloed

IPC: C23C16/44 ,  C23C16/34 ,  C23C16/455 ,  C23C16/458 ,  C23C16/52

Abstract: A chemical vapor deposition furnace for depositing silicon nitride films is disclosed. The furnace includes a process chamber elongated in a substantially vertical direction and a wafer boat for supporting a plurality of wafers in the process chamber. A process gas injector inside the process chamber is provided with vertically spaced gas injection holes to provide gas introduced at a feed end in an interior of the process gas injector to the process chamber. A valve system connected to the feed end of the process gas injector is being constructed and arranged to connect a source of a silicon precursor and a nitrogen precursor to the feed end for depositing silicon nitride layers. The valve system may connect the feed end of the process gas injector to a cleaning gas system to provide a cleaning gas to remove silicon nitride from the process gas injector and/or the process chamber.

公开(公告)号：US11996289B2

公开(公告)日：2024-05-28

申请号：US17141360

申请日：2021-01-05

Applicant: ASM IP Holding B.V.

Inventor： Amir Kajbafvala ,  Joe Margetis ,  Xin Sun ,  David Kohen ,  Dieter Pierreux

IPC: C23C16/24 ,  C23C16/08 ,  C23C16/42 ,  C23C16/455 ,  C23C16/52 ,  C30B25/16 ,  C30B25/18 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/0262 ,  C23C16/08 ,  C23C16/24 ,  C23C16/42 ,  C23C16/45523 ,  C23C16/52 ,  C30B25/165 ,  C30B25/18 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: Methods and systems for forming structures including one or more layers comprising silicon germanium and one or more layers comprising silicon are disclosed. Exemplary methods can include using a surfactant, using particular precursors, and/or using a transition step to improve an interface between adjacent layers comprising silicon germanium and comprising silicon.

公开(公告)号：US20240133030A1

公开(公告)日：2024-04-25

申请号：US18491546

申请日：2023-10-19

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Theodorus G.M. Oosterlaken

IPC: C23C16/455

CPC classification number: C23C16/45527 ,  C23C16/45544

Abstract: A method and system for depositing a material on one or more substrates by atomic layer deposition. The method comprising a step of performing a pulse (1) of a precursor of said material, wherein at least one of the average flow rate (f) and the average partial pressure (r) of said precursor over a first half (2) of the pulse (1) is higher than over a second half (3) of the pulse (1).

公开(公告)号：US11629407B2

公开(公告)日：2023-04-18

申请号：US16797346

申请日：2020-02-21

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Werner Knaepen ,  Bert Jongbloed ,  Jeroen Fluit

IPC: C23C16/48 ,  C23C16/455 ,  C23C16/44 ,  C23C16/458

Abstract: The disclosure relates to a substrate processing apparatus, comprising: a first reactor constructed and arranged to process a rack with a plurality of substrates therein; a second reactor constructed and arranged to process a substrate; and, a substrate transfer device constructed and arranged to transfer substrates to and from the first and second reactor. The second reactor may be provided with an illumination system constructed and arranged to irradiate ultraviolet radiation within a range from 100 to 500 nanometers onto a top surface of at least a substrate in the second reactor.

公开(公告)号：US20210407789A1

公开(公告)日：2021-12-30

申请号：US17352555

申请日：2021-06-21

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed ,  Kelly Houben ,  Werner Knaepen ,  Wilco Verweij

IPC: H01L21/02 ,  H01L27/11582

Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

公开(公告)号：US20210371978A1

公开(公告)日：2021-12-02

申请号：US17329829

申请日：2021-05-25

Applicant: ASM IP HOLDING B.V.

Inventor： Eric James Shero ,  Dieter Pierreux ,  Bert Jongbloed ,  Werner Knaepen ,  Charles Dezelah ,  Qi Xie ,  Petri Raisanen ,  Hannu A. Huotari ,  Paul Ma ,  Vamsi Paruchuri

IPC: C23C16/455 ,  C23C16/34

Abstract: Direct liquid injection systems and vapor deposition systems including direct liquid injection systems are disclosed. Exemplary direct liquid injection systems and related vapor deposition systems can be configured for forming vanadium containing layer on a substrate by cyclical deposition processes.

公开(公告)号：US20190304821A1

公开(公告)日：2019-10-03

申请号：US15940759

申请日：2018-03-29

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Werner Knaepen ,  Bert Jongbloed ,  Cornelis Thaddeus Herbschleb ,  Hessel Sprey

IPC: H01L21/673 ,  H01L21/306 ,  H01L21/02 ,  C23C16/48 ,  H01L21/67

Abstract: The invention relates to a substrate rack and a substrate processing system for processing substrates in a reaction chamber. The substrate rack may be used for introducing a plurality of substrates in the reaction chamber. The substrate rack may have a plurality of spaced apart substrate holding provisions configured to hold the substrates in a spaced apart relationship. The rack may have an illumination system to irradiate radiation with a range from 100 to 500 nanometers onto a top surface of the substrates.

公开(公告)号：US20180122959A1

公开(公告)日：2018-05-03

申请号：US15726959

申请日：2017-10-06

Applicant: ASM IP Holding B.V.

Inventor： Pauline Calka ,  Qi Xie ,  Dieter Pierreux ,  Bert Jongbloed

IPC: H01L29/792 ,  H01L21/02 ,  H01L27/11524 ,  C23C16/34 ,  H01L29/66 ,  H01L27/11551

CPC classification number: H01L29/792 ,  C23C16/303 ,  C23C16/34 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02227 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0234 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833

Abstract: A semiconductor device and method for manufacturing the semiconductor device are disclosed. Specifically, the semiconductor device may include a charge trapping layer with improved retention and speed for VNAND applications. The charge trapping layer may comprise an aluminum nitride (AlN) or aluminum oxynitride (AlON) layer.

公开(公告)号：US09887082B1

公开(公告)日：2018-02-06

申请号：US15222715

申请日：2016-07-28

Applicant: ASM IP Holding B.V.

Inventor： Viljami Pore ,  Werner Knaepen ,  Bert Jongbloed ,  Dieter Pierreux ,  Gido Van Der Star ,  Toshiya Suzuki

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/50 ,  H01L21/762

CPC classification number: H01L21/0228 ,  C23C16/45525 ,  C23C16/50 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/76224

Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.

公开(公告)号：US20160240373A1

公开(公告)日：2016-08-18

申请号：US14621174

申请日：2015-02-12

Applicant: ASM IP Holding B.V.

Inventor： Fu Tang ,  Michael Givens ,  Qi Xie ,  Jan Willem Maes ,  Bert Jongbloed ,  Radko G. Bankras ,  Theodorus G.M. Oosterlaken ,  Dieter Pierreux ,  Werner Knaepen ,  Harald B. Profijt ,  Cornelius A. van der Jeugd

IPC: H01L21/02

CPC classification number: H01L21/02236 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/02238

Abstract: In some embodiments, an oxide layer is grown on a semiconductor substrate by oxidizing the semiconductor substrate by exposure to hydrogen peroxide at a process temperature of about 500° C. or less. The exposure to the hydrogen peroxide may continue until the oxide layer grows by a thickness of about 1 Å or more. Where the substrate is a germanium substrate, while oxidation using H2O has been found to form germanium oxide with densities of about 4.25 g/cm3, oxidation according to some embodiments can form an oxide layer with a density of about 6 g/cm3 or more (for example, about 6.27 g/cm3). In some embodiments, another layer of material is deposited directly on the oxide layer. For example, a dielectric layer may be deposited directly on the oxide layer.

Abstract translation: 在一些实施例中，通过在约500℃或更低的工艺温度下暴露于过氧化氢来氧化半导体衬底，在半导体衬底上生长氧化物层。 暴露于过氧化氢可持续到氧化层生长约1埃以上的厚度。 当衬底是锗衬底时，虽然已经发现使用H 2 O的氧化形成密度为4.25g / cm 3的氧化锗，但是根据一些实施方案的氧化可以形成密度为约6g / cm 3或更高的氧化物层 例如约6.27g / cm 3）。 在一些实施例中，另一层材料直接沉积在氧化物层上。 例如，介电层可以直接沉积在氧化物层上。