公开(公告)号：US20180308686A1

公开(公告)日：2018-10-25

申请号：US16018692

申请日：2018-06-26

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  David de Roest ,  Jacob Woodruff ,  Michael Eugene Givens ,  Jan Willem Maes ,  Timothee Blanquart

IPC: H01L21/02 ,  H01L29/417 ,  H01L29/36 ,  H01L21/265

Abstract: A method for improving source/drain performance through conformal solid state doping and its resulting device are disclosed. Specifically, the doping takes place through an atomic layer deposition of a dopant layer. Embodiments of the invention may allow for an increased doping layer, improved conformality, and reduced defect formation, in comparison to alternate doping methods, such as ion implantation or epitaxial doping.

公开(公告)号：US20170306478A1

公开(公告)日：2017-10-26

申请号：US15135224

申请日：2016-04-21

Applicant: ASM IP Holding B.V.

Inventor： Petri Raisanen ,  Eric Shero ,  Suvi Haukka ,  Robert Brennan Milligan ,  Michael Eugene Givens

IPC: C23C16/38 ,  C23C16/455

CPC classification number: C23C16/38 ,  C23C16/45523 ,  C23C16/45525

Abstract: A method for depositing a metal boride film onto a substrate is disclosed. In particular, the method comprises pulsing a metal halide precursor onto the substrate and pulsing a boron compound precursor onto the substrate. A reaction between the metal halide precursor and the boron compound precursor forms a metal boride film. Specifically, the method discloses forming a tantalum boride (TaB2) or a niobium boride (NbB2) film.

公开(公告)号：US20170259298A1

公开(公告)日：2017-09-14

申请号：US15064404

申请日：2016-03-08

Applicant: ASM IP Holding B.V.

Inventor： Jacob Huffman Woodruff ,  Michael Eugene Givens ,  Bed Sharma ,  Petri Räisänen

IPC: B05D1/00

CPC classification number: B05D1/60 ,  B05D2203/30 ,  C23C16/04 ,  C23C16/42 ,  C23C16/45525 ,  H01L21/285

Abstract: Processes are provided for selectively depositing a metal silicide material on a first H-terminated surface of a substrate relative to a second, different surface of the same substrate. In some aspects, methods of forming a metal silicide contact layer for use in integrated circuit fabrication are provided.

公开(公告)号：US20160372543A1

公开(公告)日：2016-12-22

申请号：US14741246

申请日：2015-06-16

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Fu Tang ,  Michael Eugene Givens ,  Jan Willem Maes

IPC: H01L29/06 ,  H01L29/51 ,  H01L29/40

CPC classification number: H01L29/517 ,  H01L21/28255 ,  H01L21/28264 ,  H01L29/513 ,  H01L29/66568

Abstract: In some aspects, methods of forming a metal selenide or metal telluride thin film are provided. According to some methods, a metal selenide or metal telluride thin film is deposited on a substrate in a reaction space in a cyclical deposition process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase selenium or tellurium reactant. In some aspects, methods of forming three-dimensional architectures on a substrate surface are provided. In some embodiments, the method includes forming a metal selenide or metal telluride interface layer between a substrate and a dielectric. In some embodiments, the method includes forming a metal selenide or metal telluride dielectric layer between a substrate and a conductive layer.

Abstract translation: 在一些方面，提供了形成金属硒化物或金属碲化物薄膜的方法。 根据一些方法，金属硒化物或金属碲化物薄膜在循环沉积过程中在反应空间中沉积在基底上，其中至少一个循环包括交替地并且顺序地将基底与第一气相金属反应物接触， 气相硒或碲反应物。 在一些方面，提供了在衬底表面上形成三维结构的方法。 在一些实施方案中，该方法包括在基材和电介质之间形成金属硒化物或金属碲化物界面层。 在一些实施方案中，该方法包括在衬底和导电层之间形成金属硒化物或金属碲化物电介质层。

公开(公告)号：US20140027884A1

公开(公告)日：2014-01-30

申请号：US13941216

申请日：2013-07-12

Applicant: ASM IP Holding B.V.

Inventor： Fu Tang ,  Michael Eugene Givens ,  Qi Xie ,  Petri Raisanen

IPC: H01L21/02 ,  H01L21/67 ,  H01L23/02

CPC classification number: H01L23/3171 ,  C23C16/4405 ,  C23C16/45544 ,  H01L21/02178 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/306 ,  H01L21/67011 ,  H01L23/02 ,  H01L23/29 ,  H01L23/293 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase sulfur precursor to passivate the high-mobility semiconductor surface.

Abstract translation: 公开了用于钝化高迁移率半导体的表面的改进的方法和系统以及使用这些方法形成的结构和器件。 该方法包括向反应器的室提供高迁移率半导体表面，并将高迁移率半导体表面暴露于气相硫前体以钝化高迁移率半导体表面。

公开(公告)号：US20250132149A1

公开(公告)日：2025-04-24

申请号：US18918187

申请日：2024-10-17

Applicant: ASM IP Holding B.V.

Inventor： Aditya Chauhan ,  Vivek Koladi Mootheri ,  Lorenzo Bottiglieri ,  Andrea IIIiberi ,  Michael Eugene Givens

IPC: H01L21/02 ,  C23C16/44 ,  C23C16/455 ,  H01L29/786

Abstract: Methods for forming hydrogen barriers for, for example, channel layers in thin film transistors. The hydrogen barriers can comprise doped dielectrics such as magnesium-doped aluminum oxide. Further described are related structures and systems.

公开(公告)号：US20250109492A1

公开(公告)日：2025-04-03

申请号：US18900427

申请日：2024-09-27

Applicant: ASM IP Holding B.V.

Inventor： Patricio Eduardo Romero ,  Charles Dezelah ,  Michael Eugene Givens ,  Giuseppe Alessio Verni

IPC: C23C16/30 ,  C23C16/44

Abstract: A method, system and apparatus are disclosed for depositing a threshold voltage shifting layer comprising an oxygen-free metal sulfide on a substrate, wherein the depositing further comprises, providing a substrate having a surface within a reaction chamber, a) providing an oxygen-free precursor comprising a metal to the reaction chamber to contact the surface, b) providing an oxygen-free, sulfur-containing reactant to the reaction chamber to contact the surface, c) purging the reaction chamber and repeating operations a), b) or c) or any combination thereof until the threshold voltage shifting layer of a predetermined thickness is deposited on the surface.

公开(公告)号：US12169361B2

公开(公告)日：2024-12-17

申请号：US16931275

申请日：2020-07-16

Applicant: ASM IP Holding B.V.

Inventor： Ivo Raaijmakers ,  Daniele Piumi ,  Ivan Zyulkov ,  David Kurt de Roest ,  Michael Eugene Givens

IPC: H01L21/311 ,  G03F7/16

Abstract: A substrate processing method and apparatus to create a sacrificial masking layer is disclosed. The layer is created by providing a first precursor selected to react with one of a radiation modified and unmodified layer portion and to not react with the other one of the radiation modified and unmodified layer portion on a substrate in a reaction chamber to selectively grow the sacrificial masking layer.

公开(公告)号：US12094936B2

公开(公告)日：2024-09-17

申请号：US18376014

申请日：2023-10-03

Applicant: ASM IP Holding B.V.

Inventor： Fu Tang ,  Peng-Fu Hsu ,  Michael Eugene Givens ,  Qi Xie

IPC: H01L29/40 ,  C23C16/40 ,  H01L21/02 ,  H01L21/28 ,  H01L29/161 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/408 ,  C23C16/401 ,  C23C16/403 ,  H01L21/02145 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/28158 ,  H01L29/161 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/78

Abstract: Methods for forming a metal silicate film on a substrate in a reaction chamber by a cyclical deposition process are provided. The methods may include: regulating the temperature of a hydrogen peroxide precursor below a temperature of 70° C. prior to introduction into the reaction chamber, and depositing the metal silicate film on the substrate by performing at least one unit deposition cycle of a cyclical deposition process. Semiconductor device structures including a metal silicate film formed by the methods of the disclosure are also provided.

公开(公告)号：US20240234129A1

公开(公告)日：2024-07-11

申请号：US18402950

申请日：2024-01-03

Applicant: ASM IP Holding B.V.

Inventor： Charles Dezelah ,  Michael Eugene Givens ,  Eric Jen Cheng Liu ,  Eric James Shero ,  Fu Tang ,  Marko Tuominen ,  Eva Elisabeth Tois ,  Andrea Illiberi ,  Tatiana Ivanova ,  Paul Ma ,  Gejian Zhao

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02178 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/31111

Abstract: Methods and systems for forming structure comprising a threshold voltage tuning layer are disclosed. Exemplary methods include providing a treatment reactant to a reaction chamber to form a treated surface on the substrate surface and depositing threshold voltage tuning material overlying the treated surface. Additionally or alternatively, exemplary methods can include direct formation of metal silicide layers. Additionally or alternatively, exemplary methods can include use of an etchant.