公开(公告)号：US06400171B2

公开(公告)日：2002-06-04

申请号：US09273895

申请日：1999-03-22

申请人： Andres Bryant ,  William Clark ,  Edward J. Nowak ,  Minh Tong

发明人： Andres Bryant ,  William Clark ,  Edward J. Nowak ,  Minh Tong

IPC分类号： G01R3128

CPC分类号： G01R31/3004 ,  G01R31/2856

摘要： A circuit and a method for automatically detecting an operating condition of an integrated circuit chip and for automatically outputting a control signal in response to automatically detecting one of at least two said operating conditions. With the preferred embodiment, FET off currents are reduced during burn-in of a CMOS integrated chip. This is done by a compact, local sensing circuit. The sensing circuit is off during the normal chip operation, and the sensing circuit is only used where needed to provide a local signal to cut down excessive FET off currents. The sensing circuit preferred embodiment is designed with an NFET bandgap device that employs a novel layout approach.

摘要翻译： 一种用于自动检测集成电路芯片的工作状态并响应于自动检测至少两个所述操作条件之一而自动输出控制信号的电路和方法。 利用优选实施例，在CMOS集成芯片的老化期间，FET截止电流减小。 这是通过紧凑的局部感测电路完成的。 感测电路在正常芯片操作期间关闭，并且感测电路仅在需要时用于提供本地信号以减少过量的FET截止电流。 感测电路优选实施例设计有采用新颖布局方法的NFET带隙器件。

公开(公告)号：US06281593B1

公开(公告)日：2001-08-28

申请号：US09455554

申请日：1999-12-06

申请人： Jeffrey Scott Brown ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Steven Howard Voldman

发明人： Jeffrey Scott Brown ,  Andres Bryant ,  Robert J. Gauthier, Jr. ,  Steven Howard Voldman

IPC分类号： H01L27088

CPC分类号： H01L29/78615 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76243

摘要： A body contact to a SOI device is created by providing a deeper buried oxide region for providing connection to the FET body.

摘要翻译： 通过提供更深的掩埋氧化物区域来提供与FET体的连接来产生与SOI器件的体接触。

公开(公告)号：US06249028B1

公开(公告)日：2001-06-19

申请号：US09175308

申请日：1998-10-20

申请人： Andres Bryant ,  Edward J. Nowak ,  Minh H. Tong

发明人： Andres Bryant ,  Edward J. Nowak ,  Minh H. Tong

IPC分类号： H01L2900

CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42384 ,  H01L29/66825

摘要： An FET structure for utilization with a silicon-on-insulator semiconductor device structure. The structure includes a silicon-on-insulator substrate structure. Source and drain diffusion regions are provided on the silicon-on-insulator substrate. An FET body region is interconnected with the source and drain diffusion regions. A gate oxide region is arranged over at least a portion of the body region and the source and drain diffusion regions. A gate region is arranged over at least a portion of the gate oxide region. A diode is interconnected with and provides a conductive pathway between the gate region and the FET body region. The diode is electrically isolated from the FET source and drain regions and inversion channel by a high threshold FET region.

摘要翻译： 一种利用绝缘体上硅半导体器件结构的FET结构。 该结构包括绝缘体上硅衬底结构。 源极和漏极扩散区域设置在绝缘体上硅衬底上。 FET体区域与源极和漏极扩散区域互连。 栅极氧化物区域布置在主体区域和源极和漏极扩散区域的至少一部分上。 栅极区域布置在栅极氧化物区域的至少一部分上。 二极管与栅极区域和FET体区域互连并提供导电通路。 二极管通过高阈值FET区域与FET源极和漏极区域和反向沟道电隔离。

公开(公告)号：US08946027B2

公开(公告)日：2015-02-03

申请号：US13367725

申请日：2012-02-07

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region and source/drain (S/D) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower insulator and bottom surfaces of the S/D regions contact first portions of top surfaces of a lower silicon germanium (SiGe) layer. The FinFET structure also includes extrinsic S/D regions that contact a top surface and both side surfaces of each of the S/D regions and second portions of top surfaces of the lower SiGe layer. The FinFET structure further includes a replacement gate or gate stack that contacts a conformal dielectric, formed over a top surface and both side surfaces of the channel region.

摘要翻译： 鳍状场效应晶体管（FinFET）结构和制造FinFET的方法，其包括形成在沟道区的每个端部上的沟道区和源/漏（S / D）区的硅鳍，其中整个底表面 沟道区域接触下绝缘体的顶表面，S / D区的底表面接触下硅锗（SiGe）层的顶表面的第一部分。 FinFET结构还包括接触顶部表面的外部S / D区域和下部SiGe层的顶表面的每个S / D区域和第二部分的两个侧表面。 FinFET结构还包括形成在通道区域的顶表面和两个侧表面上的适形电介质的替代栅极或栅极堆叠。

公开(公告)号：US08698245B2

公开(公告)日：2014-04-15

申请号：US12967329

申请日：2010-12-14

申请人： Brent A. Anderson ,  Andres Bryant ,  Jiale Liang ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Jiale Liang ,  Edward J. Nowak

IPC分类号： H01L27/12

CPC分类号： H01L29/78 ,  H01L21/26506 ,  H01L29/32 ,  H01L29/66477 ,  H01L29/78612

摘要： Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.

摘要翻译： 公开了具有栅对体隧道电流区域（GTBTCR）的场效应晶体管的实施例和方法。 在一个实施例中，具有不同导电类型的相邻部分的栅极穿过半导体层的中心部分，以在中心部分内分别在具有不同导电类型的相邻部分之下分别形成沟道区域和GTBTCR。 在另一个实施例中，半导体层具有具有沟道区域的中心部分和GTBTCR。 GTBTCR包括：与沟道区相邻并掺杂相同的第一导电类型掺杂剂的较高浓度的第一注入区; 具有第二导电类型的与第一植入区相邻的第二植入区; 以及植入区域之间的增强的生成和重组区域。 具有第二导电类型的栅极穿过中心部分。

公开(公告)号：US08580601B2

公开(公告)日：2013-11-12

申请号：US13571986

申请日：2012-08-10

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  John Joseph Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  John Joseph Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L21/00

CPC分类号： H01L27/14614

摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元具有在栅极电介质上包括栅极电介质和栅电极的栅极结构。 栅极电极包括具有在栅极电介质上具有并置关系的第一和第二部分的层。 栅电极的第二部分由诸如掺杂多晶硅或金属的导体组成。 栅电极的第一部分由具有比包括第二部分的导体更高的功函的金属组成，使得栅极结构具有非对称阈值电压。

公开(公告)号：US08536018B1

公开(公告)日：2013-09-17

申请号：US13467314

申请日：2012-05-09

申请人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Michael A. Guillorn ,  Ryoji Hasumi ,  Edward J. Nowak ,  Mickey H. Yu

发明人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Michael A. Guillorn ,  Ryoji Hasumi ,  Edward J. Nowak ,  Mickey H. Yu

IPC分类号： H01L27/108

CPC分类号： H01L21/76283 ,  H01L21/76232 ,  H01L21/84

摘要： A low power maskless inter-well deep trench isolation structure and methods of manufacture such structure are provided. A method includes depositing a plurality of layers over a substrate, and forming a layer over the plurality of layers. The method also includes forming well structures in the substrate, and forming sidewall spacers at opposing sides of the layer. The method further includes forming a self-aligned deep trench in the substrate to below the well structures, by removing the sidewall spacers and portions of the substrate aligned with an opening formed by the removal of the sidewall spacers. The method also includes forming a shallow trench in alignment with the deep trench. The method further includes forming shallow trench isolation structures and deep trench isolation structures by filling the shallow trench and the deep trench with insulator material.

摘要翻译： 提供了一种低功率无掩膜深沟槽隔离结构及其制造方法。 一种方法包括在衬底上沉积多个层，并在多个层上形成层。 该方法还包括在衬底中形成阱结构，以及在层的相对侧形成侧壁间隔物。 该方法还包括通过去除侧壁间隔件和与通过去除侧壁间隔件形成的开口对准的衬底的部分，将衬底中的自对准深沟槽形成在阱结构下方。 该方法还包括形成与深沟槽对准的浅沟槽。 该方法还包括通过用绝缘体材料填充浅沟槽和深沟槽来形成浅沟槽隔离结构和深沟槽隔离结构。

公开(公告)号：US08378394B2

公开(公告)日：2013-02-19

申请号：US12876343

申请日：2010-09-07

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L29/76

CPC分类号： H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

摘要： A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer, relative to a bottom of the structure. Each of the fins comprises a central semiconductor portion and conductive end portions. At least one conductive strap may be positioned within the insulator layer below the fins, relative to the bottom of the structure. The conductive strap can be perpendicular to the fins and contact the fins. The conductive strap further includes recessed portions disposed within the insulator layer, below the plurality of fins, relative to the bottom of the structure, and between each of the plurality of fins, and projected portions disposed above the insulator layer, collinear with each of the plurality of fins, relative to the bottom of the structure. The conductive strap is disposed in at least one of a source and a drain region of the semiconductor structure. A gate insulator contacts and covers the central semiconductor portion of the fins, and a gate conductor covers and contacts the gate insulator.

摘要翻译： 一种方法和半导体结构包括在衬底上的绝缘体层，相对于该结构的底部在绝缘体层之上的多个平行的鳍。 每个翅片包括中心半导体部分和导电端部。 至少一个导电带可以相对于结构的底部定位在翅片下方的绝缘体层内。 导电带可以垂直于翅片并接触翅片。 导电带还包括设置在绝缘体层内的凹部，相对于结构的底部在多个散热片的下方，以及设置在绝缘体层之上的每个散热片之间的突出部分， 多个翅片相对于结构的底部。 导电带设置在半导体结构的源极和漏极区域中的至少一个中。 栅极绝缘体接触并覆盖翅片的中心半导体部分，并且栅极导体覆盖并接触栅极绝缘体。

公开(公告)号：US20120301990A1

公开(公告)日：2012-11-29

申请号：US13571986

申请日：2012-08-10

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L31/18

CPC分类号： H01L27/14614

摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

公开(公告)号：US20120235216A1

公开(公告)日：2012-09-20

申请号：US13051510

申请日：2011-03-18

申请人： Brent A. ANDERSON ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. ANDERSON ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L31/0216 ,  G06F17/50 ,  H01L31/18

CPC分类号： H01L31/0232 ,  G06F17/5045 ,  G06F17/5054 ,  H01L27/14632 ,  H01L27/14683 ,  H01L29/66545

摘要： Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.

摘要翻译： 提供了具有镶嵌金属栅极和像素传感器单元屏蔽的半导体结构，制造方法和设计结构。 该方法包括在虚拟栅极结构上形成介电层。 该方法还包括在电介质层中形成一个或多个凹槽。 该方法还包括去除电介质层中的虚拟栅极结构以形成沟槽。 该方法还包括在沟槽中形成金属和在电介质层中形成多个凹槽以在沟槽中形成镶嵌金属栅极结构以及在一个或多个凹槽中形成一个或多个金属部件。