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    Techniques for providing multiple delay paths in a delay circuit
    61.
    发明授权
    Techniques for providing multiple delay paths in a delay circuit 有权
    在延迟电路中提供多个延迟路径的技术

    公开(公告)号：US08159277B1

    公开(公告)日：2012-04-17

    申请号：US13031129

    申请日：2011-02-18

    申请人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    发明人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00058

    摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.

    摘要翻译： 反馈回路包括相位检测器和延迟电路。 相位检测器基于延迟周期信号产生输出信号。 延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。 每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。 延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。 每个延迟电路通过不同的延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。

    Multiple data rate interface architecture
    62.
    发明授权
    Multiple data rate interface architecture 有权
    多数据速率接口架构

    公开(公告)号：US08098082B1

    公开(公告)日：2012-01-17

    申请号：US12954204

    申请日：2010-11-24

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/017581 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

    Method and apparatus for minimizing skew between signals
    63.
    发明授权
    Method and apparatus for minimizing skew between signals 有权
    用于最小化信号之间的偏差的方法和装置

    公开(公告)号：US07884619B1

    公开(公告)日：2011-02-08

    申请号：US12566157

    申请日：2009-09-24

    申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

    发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

    IPC分类号： G01R35/00 ,  G01R23/175 ,  G08B23/00 ,  H03L7/00

    CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

    摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

    摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

    Multiple data rate interface architecture
    64.
    发明授权
    Multiple data rate interface architecture 有权
    多数据速率接口架构

    公开(公告)号：US07859304B1

    公开(公告)日：2010-12-28

    申请号：US12329553

    申请日：2008-12-06

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/017581 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

    Digitally controlled delay-locked loops
    65.
    发明授权
    Digitally controlled delay-locked loops 有权
    数字控制的延迟锁定环

    公开(公告)号：US07746134B1

    公开(公告)日：2010-06-29

    申请号：US11737116

    申请日：2007-04-18

    申请人： Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong

    发明人： Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  G11C7/22 ,  G11C7/222 ,  H03L7/091

    摘要： Digitally controlled delay-locked loops can have a phase detector, control logic, and a delay chain. The control logic generates digital signals in response to an output signal of the phase detector. The delay chain generates a delay that varies in response to the digital signals. In some embodiments, the control logic maintains logic states of the digital signals constant in response to an enable signal to maintain the delay of the delay chain constant in a lock mode of the digitally controlled delay-locked loop. In other embodiments, the delay of the delay chain varies by a discrete time period in response to a change in logic states of the digital signals, and the maximum phase error between a phase of the reference clock signal and a phase of the feedback clock signal is less than the discrete time period when the digitally controlled delay-locked loop is in a lock mode.

    摘要翻译： 数字控制的延迟锁定环路可以具有相位检测器，控制逻辑和延迟链。 控制逻辑响应于相位检测器的输出信号产生数字信号。 延迟链产生响应于数字信号而变化的延迟。 在一些实施例中，响应于使能信号，控制逻辑维持数字信号的逻辑状态恒定，以在数字控制的延迟锁定环的锁定模式中保持延迟链的延迟恒定。 在其他实施例中，延迟链的延迟响应于数字信号的逻辑状态的变化以及参考时钟信号的相位与反馈时钟信号的相位之间的最大相位误差而变化离散时间段 小于数字控制延迟锁定环处于锁定模式的离散时间周期。

    High-performance memory interface circuit architecture
    66.
    发明授权
    High-performance memory interface circuit architecture 有权
    高性能存储器接口电路架构

    公开(公告)号：US07227395B1

    公开(公告)日：2007-06-05

    申请号：US11055125

    申请日：2005-02-09

    申请人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    发明人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0805

    摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

    摘要翻译： 可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。 然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置，以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

    Address control for efficient memory partition
    68.
    发明授权
    Address control for efficient memory partition 有权
    地址控制用于高效的内存分区

    公开(公告)号：US07057962B1

    公开(公告)日：2006-06-06

    申请号：US10806638

    申请日：2004-03-22

    申请人： Johnson Tan ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Joseph Huang

    发明人： Johnson Tan ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Joseph Huang

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1075

    摘要： A memory cell of a programmable device includes a memory partitioning circuit to partition a multiple port memory device into one or more single port memory partitions. The memory partitioning circuit prevents cross addressing by setting the value of one or more address lines of each memory port to a fixed value. The memory partitioning circuit holds address lines at their required values during the programmable device's normal, clear, and reset modes of operation. The behavior of the memory partitioning circuit is set by a portion of a device configuration used to configure the programmable device. The memory partitioning circuit is connected between a memory cell's address register and row or column decoders used to access the multiple port memory device. The memory partitioning circuit can also perform bit-wise inversion operations on portions of the memory addresses.

    摘要翻译： 可编程设备的存储单元包括用于将多端口存储器设备分割成一个或多个单端口存储器分区的存储器分配电路。 存储器分配电路通过将每个存储器端口的一个或多个地址线的值设置为固定值来防止交叉寻址。 存储器分配电路在可编程器件的正常，清零和复位操作模式期间将地址线保持在其所需的值。 存储器分配电路的行为由用于配置可编程器件的器件配置的一部分来设置。 存储器分配电路连接在存储单元的地址寄存器和用于访问多端口存储器件的行或列解码器之间。 存储器分配电路还可以对存储器地址的部分执行逐位反转操作。

    DQS postamble filtering
    69.
    发明授权
    DQS postamble filtering 失效
    DQS后同步码过滤

    公开(公告)号：US07031222B1

    公开(公告)日：2006-04-18

    申请号：US11046007

    申请日：2005-01-28

    申请人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

    发明人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

    IPC分类号： G11C8/00

    CPC分类号： H03K5/135 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  H03M9/00

    摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.

    摘要翻译： 用于在高速数据接口处过滤信号的电路，方法和装置。 一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。 时钟输入端口与输入单元连接或断开。 当接收到数据脉冲串时，时钟输入端口连接到输入单元。 当数据突发结束时，时钟输入端口与输入单元断开连接。 在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。 该信号随后改变指示正在接收最后一个数据位的状态。 当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。