公开(公告)号：US07287325B2

公开(公告)日：2007-10-30

申请号：US10908392

申请日：2005-05-10

申请人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01K3/10

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

公开(公告)号：US20070210448A1

公开(公告)日：2007-09-13

申请号：US11308186

申请日：2006-03-10

申请人： Keith Wong ,  Yun-Yu Wang ,  Horatio Wildman ,  Christopher Parks ,  Chih-Chao Yang

发明人： Keith Wong ,  Yun-Yu Wang ,  Horatio Wildman ,  Christopher Parks ,  Chih-Chao Yang

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure that includes a Co-containing liner disposed between an oxygen-getter layer and a metal-containing conductive material is provided. The Co-containing liner, the oxygen-getter layer and the metal-containing conductive material form MOL metallurgy where the Co-containing liner replaces a traditional TiN liner. By “Co-containing” is meant that the liner includes elemental Co alone or elemental Co and at least one of P or B. In order to provide better step coverage of the inventive Co-containing liner within a high aspect ratio contact opening, the Co-containing liner is formed via an electroless deposition process.

摘要翻译： 提供了包括设置在吸氧剂层和含金属的导电材料之间的含Co衬里的半导体结构。 含Co的内衬，吸氧剂层和含金属的导电材料形成MOL冶金，其中含Co衬垫代替了传统的TiN衬里。 “含Co”是指衬垫包括元素Co单体或元素Co以及P或B中的至少一种。为了在高纵横比接触开口内提供本发明的含Co衬垫的更好的台阶覆盖， 通过无电镀沉积工艺形成含钴内衬。

公开(公告)号：US20070063348A1

公开(公告)日：2007-03-22

申请号：US11162666

申请日：2005-09-19

申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Lawrence Clevenger ,  Yun-Yu Wang ,  Daewon Yang

发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Lawrence Clevenger ,  Yun-Yu Wang ,  Daewon Yang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76832 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.

摘要翻译： 提供了互连结构及其制造方法。 互连结构包括具有图案化开口的电介质层，设置在图案化开口中的金属特征以及覆盖金属特征的电介质盖。 电介质盖具有内部拉伸应力，该应力有助于避免在远离金属线的方向上发生电迁移，特别是当金属线具有拉伸应力时。

公开(公告)号：US20070020929A1

公开(公告)日：2007-01-25

申请号：US11460671

申请日：2006-07-28

申请人： Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

发明人： Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.

摘要翻译： 用于减少半导体器件的自对准硅化物工艺中的枝晶形成的方法包括在半导体衬底上形成硅化物金属层，所述半导体器件具有一个或多个扩散区域，一个或多个隔离区域和一个或多个栅极结构 形成在其上。 金属层的富金属部分的浓度通过向其中引入硅而降低，半导体器件退火。

公开(公告)号：US20060270245A1

公开(公告)日：2006-11-30

申请号：US10908833

申请日：2005-05-27

申请人： Richard Conti ,  Thomas Houghton ,  Michael Lofaro ,  Jeffery Maxson ,  Ann McDonald ,  Yun-Yu Wang ,  Keith Wong ,  Daewon Yang

发明人： Richard Conti ,  Thomas Houghton ,  Michael Lofaro ,  Jeffery Maxson ,  Ann McDonald ,  Yun-Yu Wang ,  Keith Wong ,  Daewon Yang

IPC分类号： H01L21/31

CPC分类号： H01L23/53238 ,  H01L21/28556 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.

摘要翻译： 本发明涉及一种用于互连结构的双层盖结构，其包括铜金属化或其它导电金属化。 这种双层盖结构包括通过无偏高密度等离子体（HDP）化学气相沉积工艺形成的第一盖层和在第一盖层上的第二盖层，其中第二盖层由偏置的高密度等离子体（bHDP ）化学气相沉积工艺。 在bHDP化学气相沉积工艺期间，将低AC偏置功率施加到衬底上以增加衬底表面上的离子轰击并引起封盖材料的再溅射，从而形成具有优异的反应离子蚀刻（RIE）的无缝第二帽层 ）选择性。

公开(公告)号：US20060113672A1

公开(公告)日：2006-06-01

申请号：US10904827

申请日：2004-12-01

申请人： Yun-Yu Wang ,  Richard Conti ,  Chung-Ping Eng ,  Matthew Nicholls

发明人： Yun-Yu Wang ,  Richard Conti ,  Chung-Ping Eng ,  Matthew Nicholls

IPC分类号： H01L23/48 ,  H01L23/58 ,  H01L23/52

CPC分类号： H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.

摘要翻译： 一种覆盖氮化物叠层，可以防止蚀刻渗透到HDP氮化物，同时保持在Cu顶部的HDP氮化物的电迁移效果。 在一个实施例中，堆叠包括第一层HDP氮化物和设置在第一层上的Si-C-H化合物的第二层。 Si-C-H化合物例如是BLoK或N-BLoK（Si-C-H-N），并且选自在通孔RIE期间具有高选择性的一组材料，使得来自下一个布线层的RIE化学不会穿透。 碳氮是关键要素。 在另一个实施例中，堆叠包括第一层HDP氮化物，随后是第二层UVN（等离子体氮化物），以及包含设置在第二层上的HDP氮化物的第三层。

公开(公告)号：US20060097167A1

公开(公告)日：2006-05-11

申请号：US10972696

申请日：2004-10-25

申请人： Anthony Domenicucci ,  Yun-Yu Wang

发明人： Anthony Domenicucci ,  Yun-Yu Wang

IPC分类号： G21K7/00

CPC分类号： H01J37/26 ,  G03H5/00 ,  H01J37/04 ,  H01J2237/0492 ,  H01J2237/1514 ,  H01J2237/2614

摘要： A method for enhancing spatial resolution of a transmission electron microscopy TEM) system configured for electron holography. In an exemplary embodiment, the method includes configuring a first lens to form an initial virtual source with respect to an incident parallel beam, the initial virtual source positioned at a back focal plane of said first lens. A second lens is configured to form an intermediate virtual source with respect to the incident parallel beam, the position of said intermediate virtual source being dependent upon a focal length of the first lens and a focal length of the second lens. A third lens is configured to form a final virtual source with respect to the incident parallel beam, wherein the third lens has a focal length such that a front focal plane of the third lens lies beyond the position of the intermediate virtual source, with respect to a biprism location.

摘要翻译： 一种用于增强电子全息术配置的透射电子显微镜TEM系统的空间分辨率的方法。 在示例性实施例中，该方法包括配置第一透镜以相对于入射平行光束形成初始虚拟光源，初始虚拟光源位于所述第一透镜的后焦平面。 第二透镜被配置为相对于入射平行光束形成中间虚拟光源，所述中间虚拟光源的位置取决于第一透镜的焦距和第二透镜的焦距。 第三透镜被配置为相对于入射平行光束形成最终的虚拟光源，其中第三透镜具有焦距，使得第三透镜的前焦面超过中间虚拟光源的位置，相对于 双棱镜位置。

公开(公告)号：US20060001162A1

公开(公告)日：2006-01-05

申请号：US11084724

申请日：2005-03-18

申请人： Ronald Schutz ,  Werner Robl ,  Rajeev Malik ,  Lawrence Clevenger ,  Oleg Gluschenkov ,  Cyril Cabral ,  Roy Iggulden ,  Yun-Yu Wang ,  Keith Wong ,  Irene McStay

发明人： Ronald Schutz ,  Werner Robl ,  Rajeev Malik ,  Lawrence Clevenger ,  Oleg Gluschenkov ,  Cyril Cabral ,  Roy Iggulden ,  Yun-Yu Wang ,  Keith Wong ,  Irene McStay

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/7685 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/76838 ,  H01L21/76855 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4941 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L2221/1078

摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.

摘要翻译： 提供集成电路（12）中的导电结构和形成该结构的方法，其包括多晶硅层（30），在多晶硅上含有钛的薄层，在钛 - 钛层上的氮化钨层（34） 并且在氮化钨层上形成钨层。 该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。 该结构经受高温处理，而在多晶硅层（30）和钨层（32）中基本不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

公开(公告)号：US08465657B2

公开(公告)日：2013-06-18

申请号：US11833283

申请日：2007-08-03

申请人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewara ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewara ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01B13/00 ,  B44C1/22

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

公开(公告)号：US07893493B2

公开(公告)日：2011-02-22

申请号：US11456326

申请日：2006-07-10

申请人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

发明人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

IPC分类号： H01L27/12 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

摘要： An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.

摘要翻译： 中间混合表面取向结构可以包括粘附到体硅衬底上的绝缘体上硅（SOI）衬底，SOI衬底的硅具有与体硅衬底不同的表面取向，并且穿透区域延伸穿过 SOI衬底到体硅衬底，穿透区域包括在氧化硅衬底上的氮化硅衬垫和从体硅衬底外延生长的硅，外延生长的硅延伸到底切到氮化硅之下的氧化硅衬底中 衬垫，其中外延生长的硅基本上是无层错的。