公开(公告)号：US20110092045A1

公开(公告)日：2011-04-21

申请号：US12975761

申请日：2010-12-22

申请人： Badih El-Kareh

发明人： Badih El-Kareh

IPC分类号： H01L21/20

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/5223 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.

摘要翻译： 提供了一种埋地去耦电容器装置和方法。 根据各种实施例，掩埋去耦电容器装置包括在绝缘体区域上具有掩埋绝缘体区域和顶部半导体区域的绝缘体上半导体衬底。 该装置实施例还包括在绝缘体上半导体衬底中的顶部半导体区域中具有掺杂区域的第一电容器板。 该装置实施例还包括在第一电容器板上的电介质材料和介电材料上的第二电容器板。 根据各种实施例，第一电容器板，电介质材料和第二电容器板形成用于集成电路的去耦电容器。

公开(公告)号：US07880267B2

公开(公告)日：2011-02-01

申请号：US11510945

申请日：2006-08-28

申请人： Badih El-Kareh

发明人： Badih El-Kareh

IPC分类号： H01L21/02

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/5223 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.

摘要翻译： 提供了一种埋地去耦电容器装置和方法。 根据各种实施例，掩埋去耦电容器装置包括在绝缘体区域上具有掩埋绝缘体区域和顶部半导体区域的绝缘体上半导体衬底。 该装置实施例还包括在绝缘体上半导体衬底中的顶部半导体区域中具有掺杂区域的第一电容器板。 该装置实施例还包括在第一电容器板上的电介质材料和介电材料上的第二电容器板。 根据各种实施例，第一电容器板，电介质材料和第二电容器板形成用于集成电路的去耦电容器。

公开(公告)号：US20090052258A1

公开(公告)日：2009-02-26

申请号：US11895505

申请日：2007-08-23

申请人： Badih El-Kareh

发明人： Badih El-Kareh

IPC分类号： G11C16/06 ,  G11C11/34 ,  G11C5/14

CPC分类号： G11C16/10 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/06 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11524

摘要： Embodiments are described for programming and erasing a memory cell by utilizing a buried select line. A voltage potential may be generated between a source-drain region and the buried select line region of the memory cell to store charge in a storage region between the source-drain and buried select line regions. The generated voltage potential causes electrons to either tunnel towards the buried storage region to store electrical charge or away from the buried storage region to discharge electrical charge.

摘要翻译： 描述了通过利用掩埋选择线来编程和擦除存储器单元的实施例。 可以在源极 - 漏极区域和存储单元的掩埋选择线区域之间产生电压电位，以将电荷存储在源极 - 漏极和埋入选择线区域之间的存储区域中。 所产生的电压电位导致电子向掩埋的存储区域隧道以存储电荷或远离掩埋的存储区域以放电电荷。

公开(公告)号：US20080308855A1

公开(公告)日：2008-12-18

申请号：US11811702

申请日：2007-06-12

申请人： Badih El-Kareh ,  Leonard Forbes

发明人： Badih El-Kareh ,  Leonard Forbes

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L27/11524 ,  G11C16/0408 ,  G11C16/10 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/66825 ,  H01L29/7881

摘要： Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them from at least those memory cells in communication with other bit lines, such as to facilitate forward-bias write operations. The dielectric isolation structures contain an upper well having a first conductivity type and a buried well having a second conductivity type. By forward biasing the junction from the buried well to the upper well, electrons can be injected into charge-storage nodes of memory cells that are contained within the dielectric isolation structures.

摘要翻译： 公开了存储器件及其编程和形成方法。 在一个实施例中，存储器件具有包含在介质隔离结构内的存储器单元，以将它们与至少与其它位线通信的那些存储器单元隔离，以便于正向偏置写入操作。 电介质隔离结构包含具有第一导电类型的上阱和具有第二导电类型的掩埋阱。 通过将接头从掩埋阱向上偏置到上阱，电子可以被注入到包含在介质隔离结构内的存储器单元的电荷存储节点中。

公开(公告)号：US20080227262A1

公开(公告)日：2008-09-18

申请号：US11717462

申请日：2007-03-13

申请人： Badih El-Kareh ,  Leonard Forbes ,  Kie Y. Ahn

发明人： Badih El-Kareh ,  Leonard Forbes ,  Kie Y. Ahn

IPC分类号： H01L21/331 ,  H01L27/082

CPC分类号： H01L29/732 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/7371 ,  H03K17/60

摘要： Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.

摘要翻译： 已经示出了用于使用和形成垂直基极连接的双极晶体管的方法，装置和系统。 在本公开的实施例中的垂直基极连接的双极晶体管由CMOS制造技术形成，其在保持双极晶体管的高性能特性的同时降低晶体管尺寸。

公开(公告)号：US6114736A

公开(公告)日：2000-09-05

申请号：US351808

申请日：1999-07-12

申请人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

发明人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L23/283

CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6656 ,  H01L2924/0002 ,  Y10S257/916

摘要： A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

摘要翻译： 在其上形成有N阱的P掺杂半导体衬底上形成MOSFET器件，在N阱中形成一对隔离区，其中形成在N阱上方的栅氧化层。 FET器件在N阱内形成有源极和漏极区，以及形成在栅极氧化物层上方的与栅极和漏极区对准的栅电极。 栅电极包括一叠层。 在栅氧化层上形成多晶硅层。 在具有约5nm至约20nm的厚度的多晶硅层上形成氮化钨掺杂剂阻挡层，并且在氮化钨层上形成硅化钨层。

公开(公告)号：US6008083A

公开(公告)日：1999-12-28

申请号：US820930

申请日：1997-03-19

申请人： Terry J. Brabazon ,  Badih El-Kareh ,  Stuart R. Martin ,  Matthew J. Rutten ,  Carter W. Kaanta

发明人： Terry J. Brabazon ,  Badih El-Kareh ,  Stuart R. Martin ,  Matthew J. Rutten ,  Carter W. Kaanta

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242

CPC分类号： H01L28/40 ,  H01L21/76895

摘要： A precision analog metal-metal capacitor is fabricated by forming a first capacitor plate in an insulation layer by forming a trench therein, depositing metal within the trench and planarizing the device. A thin dielectric layer is then deposited and patterned over the first capacitor plate. A second insulator is then deposited over the device and discrete openings etched therein to expose the insulation layer and first metal plate. Metal is deposited within the openings and planarized, thereby forming a contact to the first metal plate and the second metal plate of the capacitor.

摘要翻译： 通过在绝缘层中形成第一电容器板，在其中形成沟槽，在沟槽内沉积金属并使器件平坦化来制造精密模拟金属 - 金属电容器。 然后在第一电容器板上沉积并图案化薄介电层。 然后将第二绝缘体沉积在器件上并且在其中蚀刻的离散开口露出绝缘层和第一金属板。 金属沉积在开口内并平坦化，从而与电容器的第一金属板和第二金属板形成接触。

公开(公告)号：US5539229A

公开(公告)日：1996-07-23

申请号：US365729

申请日：1994-12-28

申请人： Wendell P. Noble, Jr ,  Ashwin K. Ghatalia ,  Badih El-Kareh

发明人： Wendell P. Noble, Jr ,  Ashwin K. Ghatalia ,  Badih El-Kareh

IPC分类号： H01L21/8242 ,  H01L27/08 ,  H01L29/00 ,  H01L29/76

CPC分类号： H01L27/10861

摘要： A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.

摘要翻译： 一种半导体结构，包括具有栅极导体的晶体管，栅极导体具有由凸起的隔离结构（例如STI）限定的第一和第二边缘。 源极扩散与第三边缘自对准，漏极扩散与栅电极的第四边缘自对准。

公开(公告)号：US5273913A

公开(公告)日：1993-12-28

申请号：US980155

申请日：1992-11-23

申请人： Sridhar Divakaruni ,  Badih El-Kareh ,  Eric D. Johnson

发明人： Sridhar Divakaruni ,  Badih El-Kareh ,  Eric D. Johnson

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/265

CPC分类号： H01L29/6625 ,  H01L21/28525

摘要： A high performance PNP lateral bipolar transistor is described, incorporating at least two trenches extending from the upper P.sup.- surface of a semiconductor substrate almost to a buried N.sup.+ layer. The floor of one trench is heavily N-doped to establish a connection between the buried N.sup.+ layer and an N.sup.- diffusion in the walls of the trench. When the trenches are backfilled with P.sup.+ polysilicon a lateral PNP is formed having a buried base contact.

摘要翻译： 描述了一种高性能PNP横向双极晶体管，其包括从半导体衬底的上P-表面几乎延伸到掩埋的N +层的至少两个沟槽。 一个沟槽的底部被大量N掺杂以在掩埋的N +层和沟槽的壁中的N-扩散之间建立连接。 当沟槽用P +多晶硅回填时，形成具有掩埋基底接触的横向PNP。

公开(公告)号：US4476623A

公开(公告)日：1984-10-16

申请号：US279377

申请日：1981-07-01

申请人： Badih El-Kareh

发明人： Badih El-Kareh

IPC分类号： G11C11/404 ,  H01L21/74 ,  H01L21/763 ,  H01L27/02 ,  H01L27/102 ,  H01L21/302 ,  H01L21/76

CPC分类号： H01L21/743 ,  G11C11/404 ,  H01L21/763 ,  H01L27/0233 ,  H01L27/1023 ,  Y10S438/901

摘要： This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP transistor. By using the PNP transistor as a read transistor and the NPN as a write transistor, the cell, when made in integrated form, utilizes the cell isolation capacitance to enhance the stored information without increasing the parasitic capacitances in the cell. This cell isolation capacitance can be enhanced by trenching between each cell in the array, oxidizing the trench walls and backfilling the trench with semiconductor material thereby obtaining greater contrast between 0 and 1 signals. This cell is especially useful in memory arrays.

摘要翻译： 这描述了一种具有增加的介电节点电容的新颖的双极型动力单元阵列及其制作方法。 在所描述的单元中，PNP晶体管驱动NPN晶体管，使得信息被存储在PNP晶体管的基极节点电容上。 通过使用PNP晶体管作为读晶体管和NPN作为写晶体管，当以积分形式制造时，该单元利用单元隔离电容来增强存储的信息而不增加单元中的寄生电容。 可以通过在阵列中的每个单元之间的沟槽化来增强该单元隔离电容，氧化沟槽壁并用半导体材料回填沟槽，从而获得0和1信号之间的较大的对比度。 这个单元格对于存储器阵列特别有用。