公开(公告)号：US20090267668A1

公开(公告)日：2009-10-29

申请号：US12394846

申请日：2009-02-27

申请人： Chia-Liang Lin

发明人： Chia-Liang Lin

IPC分类号： H03L7/00

CPC分类号： H03K5/133 ,  H03K5/1504 ,  H03K2005/00065 ,  H03K2005/00071 ,  H03K2005/00084

摘要： Apparatus and methods are provided for calibration within a delay chain. In various embodiments, such apparatus and techniques can be used to address delay mismatch, but are not limited to such applications. Additional apparatus, systems, and methods are disclosed.

摘要翻译： 提供了用于在延迟链内进行校准的装置和方法。 在各种实施例中，这种装置和技术可以用于解决延迟失配，但不限于这种应用。 公开了附加装置，系统和方法。

公开(公告)号：US20090074125A1

公开(公告)日：2009-03-19

申请号：US12210190

申请日：2008-09-13

申请人： Chia-Liang Lin

发明人： Chia-Liang Lin

IPC分类号： H03D3/24

CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/0995 ,  H03L2207/50 ,  H03M1/745

摘要： A clock-data recovery (CDR) that employs a time-interleaved scheme is disclosed. the circuit comprises: a time-interleaved sampler/phase-detector circuit for receiving an input voltage signal and a plurality of clock signals and outputting N-bit data and N phase signals, wherein N is an integer greater than 1; a control circuit, coupled to the time-interleaved sampler/phase-detector circuit, for receiving the N phase signals and converting the N phase signals into a control signal; and a controlled oscillator, coupled to the control circuit, for generating the plurality of clock signals under the control of the control signal. The CDR is used to relax circuit speed requirement by time-interleaving phase detection by using a multi-phase lower speed circuit.

摘要翻译： 公开了采用时间交织方案的时钟数据恢复（CDR）。 所述电路包括：时间交织采样器/相位检测器电路，用于接收输入电压信号和多个时钟信号并输出​​N位数据和N相信号，其中N是大于1的整数; 耦合到时间交织采样器/相位检测器电路的控制电路，用于接收N相信号并将N相信号转换成控制信号; 以及耦合到控制电路的受控振荡器，用于在控制信号的控制下产生多个时钟信号。 CDR用于通过使用多相低速电路的时间交织相位检测来放松电路速度要求。

公开(公告)号：US07492297B2

公开(公告)日：2009-02-17

申请号：US11738965

申请日：2007-04-23

申请人： Chia-Liang Lin

发明人： Chia-Liang Lin

IPC分类号： H03M1/66

CPC分类号： H03M1/069 ,  H03M1/682 ,  H03M1/687 ,  H03M1/742 ,  H03M1/806

摘要： A digitally controlled analog circuit comprises a finite state machine configured for receiving a digital input word and generating at least two digital codes in a manner determined by a state of the finite state machine. The digital codes are decoded into respective sets of binary data. The sets of binary data control respective switched-circuit arrays to generate an analog output corresponding to the digital input word. To establish a monotonic function between the digital input word and the analog output during steady state operations, the finite state machine switches states when a wrap-around condition is detected for one of the digital codes. The finite state machine uses different sets of equations in different states to derive the digital codes.

摘要翻译： 数字控制模拟电路包括有限状态机，其配置用于接收数字输入字，并以由有限状态机的状态确定的方式生成至少两个数字代码。 数字码被解码成各自的二进制数据集。 二进制数据组控制各个开关电路阵列以产生对应于数字输入字的模拟输出。 为了在稳态操作期间在数字输入字和模拟输出之间建立单调函数，当检测到数字代码之一时，有限状态机切换状态。 有限状态机在不同状态下使用不同的方程组来导出数字代码。

公开(公告)号：US20080252373A1

公开(公告)日：2008-10-16

申请号：US12101203

申请日：2008-04-11

申请人： Hong Yean Hsieh ,  Chia-Liang Lin

发明人： Hong Yean Hsieh ,  Chia-Liang Lin

IPC分类号： H03F3/45

CPC分类号： H03F1/26 ,  H03F3/45192 ,  H03F2203/45646

摘要： A low flicker noise operational amplifier comprises two circuit branches of the same topology and a plurality of current source pairs. For each current source pair, the two current sources are commutatively steered into the two circuit branches via two sets of differential pair in a manner controlled by a pair of complementary logical signal.

摘要翻译： 低闪烁噪声运算放大器包括相同拓扑的两个电路分支和多个电流源对。 对于每个电流源对，两个电流源以由一对互补逻辑信号控制的方式经由两组差分对被相互导向到两个电路分支中。

公开(公告)号：US20080100372A1

公开(公告)日：2008-05-01

申请号：US11553452

申请日：2006-10-26

申请人： Chia-Liang Lin

发明人： Chia-Liang Lin

IPC分类号： H03K5/00

CPC分类号： H03H2/00 ,  H03H2250/00

摘要： A filter of an adjustable frequency response comprises a plurality of filters having a plurality of distinct frequency responses, respectively. These filters receive a common input signal and generate a plurality of intermediate signals, respectively. A multiplexing circuit is used to select one of these intermediate signals as a filtered signal. The multiplexing circuit is controlled by a control signal that is related to a state of the filtered signal.

摘要翻译： 可调频率响应的滤波器分别包括具有多个不同频率响应的多个滤波器。 这些滤波器接收公共输入信号并分别产生多个中间信号。 复用电路用于选择这些中间信号之一作为滤波信号。 复用电路由与滤波信号的状态有关的控制信号控制。

公开(公告)号：US07233270B2

公开(公告)日：2007-06-19

申请号：US11164491

申请日：2005-11-25

申请人： Chia-Liang Lin

发明人： Chia-Liang Lin

IPC分类号： H03M1/10

CPC分类号： H03M1/0604 ,  H03M1/0624 ,  H03M1/0836 ,  H03M1/1215

摘要： A compensation method for a receiver is disclosed, the method includes: receiving and processing an incoming signal to generate an analog input signal; utilizing a time-interleaved parallel analog-to-digital converter (ADC) for converting the analog input signal to a digital input signal according to a plurality of clock signals of different phases; equalizing the digital input signal to generate a plurality of soft decision values; generating a plurality of hard decision values according to the soft decision values; calculating a plurality of error values according to the hard decision values and the soft decision values; and compensating the receiver according to at least part of the error values.

摘要翻译： 公开了一种接收机的补偿方法，该方法包括：接收和处理输入信号以产生模拟输入信号; 利用时间交错的并行模数转换器（ADC），用于根据多个不同相位的时钟信号将模拟输入信号转换成数字输入信号; 均衡数字输入信号以产生多个软判决值; 根据软判决值生成多个硬决策值; 根据硬判决值和软判决值计算多个误差值; 以及根据至少部分误差值补偿接收机。

公开(公告)号：US20070008200A1

公开(公告)日：2007-01-11

申请号：US11389990

申请日：2006-03-27

申请人： Hong-Yean Hsieh ,  Chia-Liang Lin

发明人： Hong-Yean Hsieh ,  Chia-Liang Lin

IPC分类号： H03M1/10

CPC分类号： H03M3/38

摘要： A primary delta-sigma modulator converts a continuous-time input signal into a discrete-time output sequence. A calibration circuit comprising an auxiliary delta-sigma modulator estimates percentage error in an integrator time constant and adjusts the time constant of at least one integrator in the primary delta-sigma modulator accordingly. The auxiliary delta-sigma modulator and the primary delta-sigma modulator use integrators with substantially similar circuit designs. The percentage error in the time constant of the integrator in the auxiliary delta-sigma modulator, and correspondingly the percentage error in time constant of the integrator in the primary delta-sigma modulator, is estimated by injecting a calibrating sequence into the auxiliary delta-sigma modulator and examining a correlation between an error sequence and an output sequence of the auxiliary delta-sigma modulator.

摘要翻译： 原始Δ-Σ调制器将连续时间输入信号转换成离散时间输出序列。 包括辅助Δ-Σ调制器的校准电路估计积分器时间常数中的百分比误差，并且相应地调整主Δ-Σ调制器中的至少一个积分器的时间常数。 辅助Δ-Σ调制器和主Δ-Σ调制器使用具有基本相似的电路设计的积分器。 辅助Δ-Σ调制器中积分器的时间常数百分比误差，以及相应的初级Δ-Σ调制器中积分器的时间常数百分比误差，通过将校准序列注入辅助Δ-Σ 调制器并检查辅助Δ-Σ调制器的误差序列和输出序列之间的相关性。

公开(公告)号：US20060182172A1

公开(公告)日：2006-08-17

申请号：US11230856

申请日：2005-09-20

申请人： Chia-Liang Lin

发明人： Chia-Liang Lin

IPC分类号： H03H7/30

CPC分类号： H04L25/03057 ,  H04L2025/03363 ,  H04L2025/0349 ,  H04L2025/03617

摘要： A feedback equalizer is provided that minimizes the critical path time in a multi-level modulation receiver. The critical path is reduced by parallel operation of some summation components of the feedback equalizer. The critical path is further reduced by pre-computing coefficients for the feedback equalizer. Further, the critical path is reduced using an adaptive feedback equalizer which uses parallelism or pre-computation to calculate the feedback equalization coefficients using an adaptation engine.

公开(公告)号：US06710735B1

公开(公告)日：2004-03-23

申请号：US10464718

申请日：2003-06-17

申请人： Chia-Liang Lin

发明人： Chia-Liang Lin

IPC分类号： H03M138

CPC分类号： H03M1/089 ,  H03M1/167 ,  H03M1/44

摘要： An analog-to-digital converter (ADC) includes N stages implemented within a single integrated circuit and connected in series to form a pipeline. The first stage of the pipeline receives the analog signal as its input, and each of the first N−1 stages of the pipeline supplies an analog residue signal as input to a next succeeding stage of the pipeline. Each stage includes an amplifier for amplifying its input signal to produce a sample voltage stored in an internal sampling capacitor and generates output data indicating an approximate magnitude of its stored sample voltage. The magnitude of the analog residue signal produced by each stage indicates a difference between the voltage represented by that stage's output data and its sample voltage. The amplifiers of the first N-M stages of the pipeline are powered by a higher supply voltage than the amplifiers of the last M stages of the pipeline to maximize the sample voltages in the first N-M stages, thereby reducing the influence of thermal noise on the sample voltages in those stages.

摘要翻译： 模数转换器（ADC）包括在单个集成电路内实现并且串联连接以形成管线的N级。 管线的第一级接收模拟信号作为其输入，并且流水线的第一N-1级中的每一级将模拟残留信号作为输入提供给管道的下一级。 每个级包括用于放大其输入信号以产生存储在内部采样电容器中的采样电压的放大器，并产生指示其存储的采样电压的近似幅度的输出数据。 每级产生的模拟残留信号的大小表示由该级输出数据表示的电压与其采样电压之间的差值。 管道的第一NM级的放大器由比管道的最后M级的放大器更高的电源电压供电，以使第一NM级中的采样电压最大化，从而减少热噪声对采样电压的影响 在这些阶段。

公开(公告)号：US06642874B1

公开(公告)日：2003-11-04

申请号：US10269594

申请日：2002-10-11

申请人： Chia-Liang Lin ,  Tzu-Hsien Sang

发明人： Chia-Liang Lin ,  Tzu-Hsien Sang

IPC分类号： H03M300

CPC分类号： H03M7/3008 ,  H03M3/326 ,  H03M3/458 ,  H03M7/3024

摘要： A sigma-delta circuit converts an analog or digital input sequence xn representing a quantity with at least p-bit resolution into an m-bit output sequence yn, where m

摘要翻译： Σ-Δ电路将表示具有至少p位分辨率的量的模拟或数字输入序列xn转换成m位输出序列yn，其中m