公开(公告)号：US10699785B2

公开(公告)日：2020-06-30

申请号：US16144771

申请日：2018-09-27

申请人： Crossbar, Inc.

发明人： Mehdi Asnaashari ,  Hagop Nazarian ,  Christophe Sucur ,  Sylvain Dubois

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C7/18 ,  G11C8/12 ,  G11C29/42 ,  G11C29/44 ,  G11C8/14 ,  G06F17/16 ,  G11C29/04

摘要： Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receiving data from an external device and for outputting data to the external device, and a second data interface for outputting data to the external device. The non-volatile memory architecture can also comprise programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, and connected to the data interface. The programmable processing elements are configured to receive stored data from the resistive random access memory array via the respective sets of bitlines or to receive external data from the external device via the data interface, and execute a logical or mathematical algorithm on the external data or the stored data and generate processed data.

公开(公告)号：US10475511B1

公开(公告)日：2019-11-12

申请号：US16193592

申请日：2018-11-16

申请人： Crossbar, Inc.

发明人： Lin Shih Liu ,  Tianhong Yan ,  Sung Hyun Jo ,  Sang Nguyen ,  Hagop Nazarian

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C7/06

摘要： Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by a single transistor, the resulting array is referred to as a 1T1R memory array. In contrast, where a group of memory cells are isolated from surrounding circuitry by a single transistor, the result is a 1TnR memory array. Because memory cells of a group are not isolated among themselves in the 1TnR case, bit disturb effects are theoretically possible when operating on a single memory cell. Read operations are disclosed for two-terminal memory devices configured to mitigate bit disturb effects, despite a lack of isolation transistors among memory cells of an array. Disclosed operations can facilitate reduced bit disturb effects even for high density two-terminal memory cell arrays.

公开(公告)号：US10347335B2

公开(公告)日：2019-07-09

申请号：US15926394

申请日：2018-03-20

申请人： Crossbar, Inc.

发明人： Mehdi Asnaashari ,  Hagop Nazarian

IPC分类号： G11C13/00 ,  G11C14/00

摘要： A retainer node circuit is provided that can retain state information of a volatile circuit element (e.g., a flip-flop, latch, switch, register, etc.) of an electronic device for planned or unplanned power-down events. The retainer node circuit can include a resistive-switching memory cell that is nonvolatile, having very fast read and write performance. Coupled with power management circuitry, the retainer node circuit can be activated to receive and store a signal (e.g., bit) output by the volatile circuit element, and activated to output the stored signal. Various embodiments disclose non-volatile retention of state information for planned shut-down events as well as unplanned shut-down events. With read and write speeds in the tens of nanoseconds, sleep mode can be provided for volatile circuit elements between clock cycles of longer time-frame applications, enabling intermittent power-down events between active periods. This enables reduction in power without loss of activity for an electronic device.

公开(公告)号：US10199093B1

公开(公告)日：2019-02-05

申请号：US15590245

申请日：2017-05-09

申请人： Crossbar, Inc.

发明人： Sang Nguyen ,  Hagop Nazarian ,  Tianhong Yan

IPC分类号： G11C16/26 ,  G11C11/419 ,  G11C8/18 ,  G11C7/10 ,  G11C11/418 ,  G11C7/06

摘要： A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state, e.g., to a defined higher resistance state or a defined lower resistance state. Other, techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that cause the state change and can do so by comparing the magnitudes or values of two particular current parameters.

公开(公告)号：US20190027219A1

公开(公告)日：2019-01-24

申请号：US16138673

申请日：2018-09-21

申请人： Crossbar, Inc.

发明人： Hagop Nazarian ,  Sung Hyun Jo

IPC分类号： G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： G11C13/0069 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/11 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/79

摘要： A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch.

公开(公告)号：US10056907B1

公开(公告)日：2018-08-21

申请号：US15593371

申请日：2017-05-12

申请人： Crossbar, Inc.

发明人： Mehdi Asnaashari ,  Hagop Nazarian ,  Sang Nguyen

IPC分类号： H03K19/17 ,  H03K19/00 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/0013 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17776

摘要： A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, coupling a second electrode of the first resistive element, and a first electrode of the second resistive element to a first terminal of a first transistor element, coupling a second terminal of the first transistor element to a first terminal of a latch, coupling a second terminal of the latch to a gate of a second transistor element, and coupling a gate of the first transistor element to a latch program signal.

公开(公告)号：US20170330622A1

公开(公告)日：2017-11-16

申请号：US15592999

申请日：2017-05-11

申请人： Crossbar, Inc.

发明人： Lin Shih Liu ,  Hagop Nazarian

IPC分类号： G11C14/00 ,  G11C13/00 ,  G11C11/419

CPC分类号： G11C14/009 ,  G11C11/412 ,  G11C11/419 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  H03K19/1776

摘要： Providing for a configuration cells for junction nodes of a field programmable gate array (FPGA) is described herein. By way of example, a configuration cell can comprise non-volatile resistive switching memory to facilitate programmable storage of data as an input to a control circuit of a junction node. The control circuit can activate or deactivate a junction node of the FPGA in response to a value of the data stored in the non-volatile resistive switching memory. The control circuit can comprise an SRAM circuit for fast operation of the junction node. Moreover, the non-volatile memory of the configuration cell facilitates fast power-up of the control circuit utilizing data stored in the resistive switching memory, and minimizes power consumption associated with storing the data.

公开(公告)号：US09633723B2

公开(公告)日：2017-04-25

申请号：US14383079

申请日：2013-05-24

申请人： Crossbar, Inc.

发明人： Sang Nguyen ,  Hagop Nazarian

IPC分类号： G11C13/00 ,  G11C5/06 ,  G11C16/26 ,  G11C7/00 ,  G11C7/06 ,  G11C11/419

CPC分类号： G11C13/004 ,  G11C11/419 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0097 ,  G11C2013/0042 ,  G11C2013/0052 ,  G11C2213/53 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79

摘要： Providing for resistive random access memory (RRAM) having high read speeds is described herein. By way of example, a RRAM memory can be powered at one terminal by a bitline, and connected at another terminal to a gate of a transistor having a low gate capacitance (relative to a capacitance of the bitline). With this arrangement, a signal applied at the bitline can quickly switch the transistor gate, in response to the RRAM memory being in a conductive state. A sensing circuit configured to measure the transistor can detect a change in current, voltage, etc., of the transistor and determine a state of the RRAM memory from the measurement. Moreover, this measurement can occur very quickly due to the low capacitance of the transistor gate, greatly improving the read speed of RRAM.

公开(公告)号：US20160268341A1

公开(公告)日：2016-09-15

申请号：US14795105

申请日：2015-07-09

申请人： Crossbar, Inc.

发明人： Hagop Nazarian ,  Sung Hyun Jo ,  Harry Yue Gee

IPC分类号： H01L27/24 ,  H01L29/66 ,  H01L45/00 ,  H01L29/423 ,  H01L49/02

CPC分类号： H01L27/2463 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C14/00 ,  G11C14/0045 ,  G11C2213/53 ,  G11C2213/79 ,  H01L27/2436 ,  H01L28/60 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/66613 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/148 ,  H01L45/1608

摘要： A high density non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A deep trench MOS (“metal-oxide-semiconductor”) transistor having a floating gate with small area relative to conventional devices can be provided, in addition to a capacitor or transistor acting as a capacitor. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. The small area floating gate of the deep trench transistor can be connected to the other side of the selector device, and a second transistor can be connected in series with the deep trench transistor.

摘要翻译： 提供了使用一个或多个易失性元件的高密度非易失性存储器件。 在一些实施例中，非易失性存储器件可以包括根据施加的电压可以处于低电阻状态或高电阻状态的电阻式两端选择器。 除了作为电容器的电容器或晶体管之外，还可以提供具有相对于常规器件具有小面积的浮动栅极的深沟槽MOS（“金属氧化物半导体”）晶体管。 电容器的第一端子可以连接到电压源，并且电容器的第二端子可以连接到选择器装置。 深沟槽晶体管的小面积浮栅可以连接到选择器件的另一侧，并且第二晶体管可以与深沟槽晶体管串联连接。

公开(公告)号：US09385319B1

公开(公告)日：2016-07-05

申请号：US14306093

申请日：2014-06-16

申请人： Crossbar, Inc.

发明人： Hagop Nazarian ,  Sung Hyun Jo

IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1641 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/148 ,  H01L45/165 ,  H01L45/1675

摘要： A resistive memory device includes a first metallic layer comprising a source of positive metallic ions, a switching media having an upper surface and a lower surface, wherein the upper surface is adjacent to the first metallic layer, wherein the switching media comprises conductive filaments comprising positive metallic ions from the source of positive metallic ions formed from the upper surface towards the lower surface, a semiconductor substrate, a second metallic layer disposed above the semiconductor substrate, a non-metallic conductive layer disposed above the second metallic layer, and an interface region between the non-metallic conductive layer and the switching media having a negative ionic charge.

摘要翻译： 电阻式存储器件包括包含正金属离子源的第一金属层，具有上表面和下表面的开关介质，其中上表面与第一金属层相邻，其中开关介质包括包含正极的导电细丝 从上表面朝向下表面形成的正金属离子源的金属离子，半导体衬底，设置在半导体衬底上方的第二金属层，设置在第二金属层上方的非金属导电层，以及界面区域 在非金属导电层和具有负离子电荷的开关介质之间。