公开(公告)号：US08043907B2

公开(公告)日：2011-10-25

申请号：US12687732

申请日：2010-01-14

申请人： Yi Ma ,  Shreyas S. Kher ,  Khaled Ahmed ,  Tejal Goyani ,  Maitreyee Mahajani ,  Jallepally Ravi ,  Yi-Chiau Huang

发明人： Yi Ma ,  Shreyas S. Kher ,  Khaled Ahmed ,  Tejal Goyani ,  Maitreyee Mahajani ,  Jallepally Ravi ,  Yi-Chiau Huang

IPC分类号： H01L21/8238

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/7881

摘要： Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate.

摘要翻译： 本发明的实施例提供了用于形成这种存储器件的存储器件和方法。 在一个实施例中，提供了一种用于在衬底上制造非易失性存储器件的方法，其包括在衬底表面上沉积第一多晶硅层，在第一多晶硅层上沉积氧化硅层，在第一多晶硅层上沉积第一氧氮化硅层 氧化硅层，在第一氧氮化硅层上沉积氮化硅层，在氮化硅层上沉积第二氮氧化硅层，以及在第二氮氧化硅层上沉积第二多晶硅层。 在一些示例中，第一多晶硅层是浮置栅极，第二多晶硅层是控制栅极。

公开(公告)号：US20100102376A1

公开(公告)日：2010-04-29

申请号：US12687732

申请日：2010-01-14

申请人： Yi Ma ,  Shreyas S. Kher ,  Khaled Ahmed ,  Tejal Goyani ,  Maitreyee Mahajani ,  Jallepally Ravi ,  Yi-Chiau Huang

发明人： Yi Ma ,  Shreyas S. Kher ,  Khaled Ahmed ,  Tejal Goyani ,  Maitreyee Mahajani ,  Jallepally Ravi ,  Yi-Chiau Huang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/7881

摘要： Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate.

摘要翻译： 本发明的实施例提供了用于形成这种存储器件的存储器件和方法。 在一个实施例中，提供了一种用于在衬底上制造非易失性存储器件的方法，其包括在衬底表面上沉积第一多晶硅层，在第一多晶硅层上沉积氧化硅层，在第一多晶硅层上沉积第一氧氮化硅层 氧化硅层，在第一氧氮化硅层上沉积氮化硅层，在氮化硅层上沉积第二氮氧化硅层，以及在第二氮氧化硅层上沉积第二多晶硅层。 在一些示例中，第一多晶硅层是浮置栅极，第二多晶硅层是控制栅极。

公开(公告)号：US20090246972A1

公开(公告)日：2009-10-01

申请号：US12057113

申请日：2008-03-27

申请人： SHREYAS S. KHER ,  Pravin K. Narwankar ,  Khaled Z. Ahmed ,  Yi Ma

发明人： SHREYAS S. KHER ,  Pravin K. Narwankar ,  Khaled Z. Ahmed ,  Yi Ma

IPC分类号： H01L21/31

CPC分类号： H01L21/31645 ,  C23C14/083 ,  C23C16/56 ,  H01L21/3141

摘要： Processes for making a high K (dielectric constant) film using an ultra-high purity hafnium containing organometallic compound are disclosed. Also described are devices incorporating high K films made with high purity hafnium containing organometallic compounds.

摘要翻译： 公开了使用含有超高纯度铪的有机金属化合物制造高K（介电常数）膜的方法。 还描述了包含用高纯度铪含有有机金属化合物制成的高K膜的装置。

公开(公告)号：US06544907B1

公开(公告)日：2003-04-08

申请号：US09689030

申请日：2000-10-12

申请人： Yi Ma ,  Edith Yang

发明人： Yi Ma ,  Edith Yang

IPC分类号： H01L2131

CPC分类号： H01L21/28211

摘要： The present invention provides a method for manufacturing a high quality oxide layer having a uniform thickness. The method includes providing a semiconductor substrate, and forming an oxide layer having a substantially uniform thickness on the semiconductor substrate, and in a zone of pressure of less than about 4 Torr or greater than about 25 Torr.

摘要翻译： 本发明提供一种具有均匀厚度的高品质氧化物层的制造方法。 该方法包括提供半导体衬底，以及在半导体衬底上形成具有基本上均匀厚度的氧化物层，以及小于约4Torr或大于约25Torr的压力区。

公开(公告)号：US06451660B1

公开(公告)日：2002-09-17

申请号：US09591037

申请日：2000-06-09

申请人： Yi Ma ,  Yih-Feng Chyan ,  Chung Wai Leung ,  Jane Qian Liu ,  Timothy Scott Campbell

发明人： Yi Ma ,  Yih-Feng Chyan ,  Chung Wai Leung ,  Jane Qian Liu ,  Timothy Scott Campbell

IPC分类号： H01L2131

CPC分类号： H01L29/66272 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02307 ,  H01L21/31675 ,  H01L29/0804

摘要： A bipolar device (10) includes an oxide layer (24) which is grown on the surface (16) of a semiconductor substrate (12) by immersing the surface in ozonated deionized water. By selecting an appropriate temperature of the water and concentration of the ozone, the thickness of the film can be maintained within fine tolerances from lot to lot, and over the surface of a wafer (W) comprising the substrate.

摘要翻译： 双极器件（10）包括通过将表面浸入臭氧化去离子水中而在半导体衬底（12）的表面（16）上生长的氧化物层（24）。 通过选择水的适当温度和臭氧的浓度，可以将薄膜的厚度保持在大量的精细公差之内，并且在包含基底的晶片（W）的表面上。

公开(公告)号：US06440829B1

公开(公告)日：2002-08-27

申请号：US09223354

申请日：1998-12-30

申请人： Pradip K. Roy ,  Yi Ma ,  Michael A. Laughery

发明人： Pradip K. Roy ,  Yi Ma ,  Michael A. Laughery

IPC分类号： H01L213205

CPC分类号： H01L29/4925 ,  H01L21/28176 ,  H01L21/28211

摘要： A method and structure providing N-profile engineering at the poly/gate oxide and gate oxide/Si interfaces of a layered polysilicon/amorphous silicon structure of a semiconductor device. NH3 annealing provides for the introduction of nitrogen to the interface, where the nitrogen suppresses Boron diffusion, improves gate oxide integrity, and reduces the sites available for trapping hot carriers which degrade device performance.

摘要翻译： 在半导体器件的分层多晶硅/非晶硅结构的多晶硅/栅极氧化物和栅极氧化物/ Si界面处提供N型构造的方法和结构。 NH3退火提供了将氮引入界面，其中氮抑制硼扩散，提高了栅极氧化物的完整性，并且减少了用于捕获热载流子的位置，这降低了器件性能。

公开(公告)号：US06281138B1

公开(公告)日：2001-08-28

申请号：US09338939

申请日：1999-06-24

申请人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

发明人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

IPC分类号： H01L2131

CPC分类号： H01L21/28185 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31612 ,  H01L29/513 ,  H01L29/518

摘要： This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer, which contains a substantial concentration of a hydrogen isotope, such as deuterium, forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps.

摘要翻译： 本发明包括在低压例如0.2-10乇下生长，沉积和生长SiO 2的三步法的新型合成，以产生用于亚0.5微米技术的高质量，坚固和可靠的栅极氧化物。 对第一层，1.0-3.0nm进行热生长以钝化Si半导体表面。 包含相当浓度的氢同位素（例如氘）的第二沉积层与第一生长层形成界面。 在沉积的氧化物层的合成致密化的第三步骤中，同时去除界面处的界面陷阱并且在存在应力容纳的情况下在Si /第一生长层界面处发生应力调制的SiO 2的生长 界面层，产生平面和应力降低的Si / SiO 2界面。 整个合成在低压（例如，0.2-10托）下进行，以减缓氧化动力学以达到超薄亚层，并且可以通过聚集所有三个步骤在单个低压炉中进行。

公开(公告)号：US06274490B1

公开(公告)日：2001-08-14

申请号：US09521268

申请日：2000-03-08

申请人： Yih-Feng Chyan ,  Yi Ma

发明人： Yih-Feng Chyan ,  Yi Ma

IPC分类号： H01L2144

CPC分类号： H01L29/518 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/324 ,  H01L21/76826 ,  H01L21/76834

摘要： The present invention provides a method of passivating a semiconductor device having a capping layer formed thereover, comprising: (1) subjecting the semiconductor device to a high pressure within a pressure chamber and (2) exposing the semiconductor device to a passivating gas. The high pressure causes the passivating gas, such as a deuterated passivating gas, to penetrate the capping layer and thereby passivate the semiconductor device. The method provided by the present invention is, therefore, particularly useful in those instances where a final passivation step is desired after the formation of the capping layer. It is believed that the hydrogen isotope bonds to dangling bond sites within the semiconductor device, which are most often present at a silicon/silicon dioxide interface. Further, because of their larger mass, these hydrogen isotope atoms are not easily removed by electron flow during the operation of the device as is the case with the lighter hydrogen atoms.

摘要翻译： 本发明提供一种钝化具有形成在其上的覆盖层的半导体器件的方法，包括：（1）使半导体器件在压力室内受到高压，以及（2）将半导体器件暴露于钝化气体。 高压使诸如氘代钝化气体的钝化气体穿透封盖层，从而钝化半导体器件。 因此，本发明提供的方法在形成覆盖层之后需要最终钝化步骤的情况下特别有用。 据信氢同位素结合到半导体器件内的悬挂键合位置，其通常存在于硅/二氧化硅界面处。 此外，由于它们的质量较大，与较轻的氢原子一样，这些氢同位素原子在器件的操作过程中不容易被电子流除去。

公开(公告)号：US5940736A

公开(公告)日：1999-08-17

申请号：US814670

申请日：1997-03-11

申请人： David C. Brady ,  Yi Ma ,  Pradip K. Roy

发明人： David C. Brady ,  Yi Ma ,  Pradip K. Roy

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/02

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L21/28211

摘要： This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO.sub.2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer 1.0-5.0 nm forms an interface to with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO.sub.2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO.sub.2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps. For light nitrogen-incorporation (

摘要翻译： 本发明包括在低压例如0.2-10乇下生长，沉积和生长SiO 2的三步法的新型合成，以产生用于亚0.5微米技术的高质量，坚固和可靠的栅极氧化物。 对第一层，1.0-3.0nm进行热生长以钝化Si半导体表面。 第二沉积层1.0-5.0nm形成与第一生长层的界面。 在沉积的氧化物层的合成致密化的第三步骤中，同时去除界面处的界面陷阱并且在应力容纳的存在下在Si /第一生长层界面处发生应力调制的SiO 2的生长 界面层，产生平面和应力降低的Si / SiO 2界面。 整个合成在低压（例如，0.2-10托）下进行，以减缓氧化动力学以达到超薄亚层，并且可以通过聚集所有三个步骤在单个低压炉中进行。 对于某些器件的轻氮掺入（<5％），通常由于提高的耐硼性和其他掺杂剂扩散性和热载流子特性而需要，因此在层叠氧化物合成的每个步骤期间都使用氧化剂中的N2O或NO。 平面和应力降低的Si / SiO 2界面特性是层叠氧化物的独特标志，其改善了栅极氧化物对ULSI处理的鲁棒性，导致器件参数（例如，阈值电压跨导），迁移率降低和对热载流子的耐受性降低 和福勒 - 诺德海姆的压力。

公开(公告)号：US11923554B2

公开(公告)日：2024-03-05

申请号：US17295053

申请日：2019-10-17

申请人： Yi Ma

发明人： Yi Ma

IPC分类号： H01M50/207 ,  H01M50/247 ,  H01M50/249

CPC分类号： H01M50/207 ,  H01M50/247 ,  H01M50/249 ,  H01M2220/20

摘要： An extruded hollow plate and an electric vehicle battery casing formed by combining the extruded hollow plates. The extruded hollow plate has a plate-shaped body having a constant cross-section, a cavity is provided inside the plate-shaped body, a protrusion and/or a groove is provided at an end of the body, the protrusion is bent downward, the groove opens upwards as a hook, and the arc surfaces forming the protrusion and the groove each comprise at least two involute surfaces. Compared with the existing battery box manufacturing process of friction stir welding, the combining and bonding connection manner has the significant advantages of rapid production speed, a low device cost, high flatness, etc.