利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

143 条记录 (耗时 0.03 秒)

    Extremely-thin silicon-on-insulator transistor with raised source/drain
    62.
    发明授权
    Extremely-thin silicon-on-insulator transistor with raised source/drain 有权
    极薄的绝缘体上硅晶体管，具有升高的源极/漏极

    公开(公告)号：US07652332B2

    公开(公告)日：2010-01-26

    申请号：US11837057

    申请日：2007-08-10

    申请人： Eduard A. Cartier ,  Steven J. Koester ,  Kingsuk Maitra ,  Amlan Majumdar ,  Renee T. Mo

    发明人： Eduard A. Cartier ,  Steven J. Koester ,  Kingsuk Maitra ,  Amlan Majumdar ,  Renee T. Mo

    IPC分类号： H01L27/01

    CPC分类号： H01L29/6659 ,  H01L21/28079 ,  H01L29/4958 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78696

    摘要： An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.

    摘要翻译： 提供了一种极薄的绝缘体上硅晶体管，其包括衬底上的掩埋氧化物层，掩埋氧化物层上方的硅层，硅层上的栅极堆叠，硅层上的氮化物衬垫， 栅堆叠，氮化物衬垫上并与其相邻的氧化物衬垫，以及升高的源/漏区。 栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。 凸起的源极/漏极区域中的每一个具有包括硅层的一部分的第一部分，与氧化物衬垫和氮化物衬垫的部分相邻的第二部分，以及在第二部分上方的第三部分。 还提供了制造极薄的绝缘体上硅晶体管的方法。

    Embedded DRAM Integrated Circuits With Extremely Thin Silicon-On-Insulator Pass Transistors
    64.
    发明申请
    Embedded DRAM Integrated Circuits With Extremely Thin Silicon-On-Insulator Pass Transistors 有权
    嵌入式DRAM集成电路与极薄的绝缘体上硅晶体管

    公开(公告)号：US20090108314A1

    公开(公告)日：2009-04-30

    申请号：US11929943

    申请日：2007-10-30

    申请人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

    发明人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

    IPC分类号： H01L21/84 ,  H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10894

    摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

    摘要翻译： 提供具有组合的存储器和逻辑功能的集成电路。 一方面，提供集成电路。 集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。

    PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION
    65.
    发明申请
    PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION 有权
    具有金属化源侧HALO区域的部分沉积SOI场效应晶体管

    公开(公告)号：US20080308867A1

    公开(公告)日：2008-12-18

    申请号：US11761568

    申请日：2007-06-12

    申请人： Jin Cai ,  Wilfried Haensch ,  Amlan Majumdar

    发明人： Jin Cai ,  Wilfried Haensch ,  Amlan Majumdar

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L29/78696 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78624

    摘要： Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.

    摘要翻译： 源极和漏极延伸区域和源极侧卤素区域和漏极侧晕圈形成在与SOI衬底上的栅极堆叠对准的顶部半导体层中。 通过成角度的离子注入，在顶部半导体层中不均匀地形成深源区和深漏区。 深源区域远离至少间隔物的外缘之一偏离以暴露半导体衬底的表面上的源延伸区域。 源金属半导体合金通过使金属层与深源区，源极延伸区和源极侧晕区的一部分反应而形成。 源极金属半导体合金与源极侧光晕区域的剩余部分相邻，从而将与源极区域连接的体接触部分连接到部分耗尽的SOI MOSFET。