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    Semiconductor structure having NFET extension last implants
    61.
    发明授权
    Semiconductor structure having NFET extension last implants 有权
    具有NFET延伸最后植入物的半导体结构

    公开(公告)号：US08546203B1

    公开(公告)日：2013-10-01

    申请号：US13551100

    申请日：2012-07-17

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Nicolas Loubet ,  Amlan Majumdar ,  Stefan Schmitz

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Nicolas Loubet ,  Amlan Majumdar ,  Stefan Schmitz

    IPC分类号： H01L21/00

    CPC分类号： H01L21/84 ,  H01L29/66628

    摘要： Method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. Low quality nitride and high quality nitride are formed on the semiconductor structure. The high quality nitride in the NFET portion is damaged by ion implantation to facilitate its removal. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The high quality nitride in the PFET portion is damaged by ion implantation to facilitate its removal. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

    摘要翻译： 形成半导体结构的方法包括具有PFET部分和NFET部分的极薄的绝缘上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，与 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。 在半导体结构上形成低质量的氮化物和高质量的氮化物。 NFET部分中的高质量氮化物被离子注入损坏以便于其去除。 在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的高质量氮化物被离子注入损坏以便于其去除。 扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

    Nanowire circuits in matched devices
    62.
    发明授权
    Nanowire circuits in matched devices 有权
    纳米线电路在匹配的设备

    公开(公告)号：US08520430B2

    公开(公告)日：2013-08-27

    申请号：US13554057

    申请日：2012-07-20

    申请人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： G11C11/00

    CPC分类号： H03K19/20 ,  B82Y10/00 ,  G11C11/412 ,  G11C11/54 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/12 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/78696

    摘要： A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire.

    摘要翻译： 存储器件包括连接到第一位线节点和接地节点的第一纳米线，具有设置在第一纳米线上的栅极的第一场效应晶体管（FET），具有设置在第一纳米线上的栅极的第二FET， 连接到电压源节点和第一输入节点的纳米线，具有设置在第二纳米线上的栅极的第三FET，连接到电压源节点的第三纳米线和第二输入节点，具有设置在第三纳米线上的栅极的第四FET 纳米线，连接到第二位线节点的第四纳米线和所述接地节点，具有设置在所述第四纳米线上的栅极的第五FET以及设置在所述第四纳米线上的栅极的第六FET。

    Nanowire tunnel field effect transistors
    63.
    发明授权
    Nanowire tunnel field effect transistors 有权
    纳米线隧道场效应晶体管

    公开(公告)号：US08324030B2

    公开(公告)日：2012-12-04

    申请号：US12778315

    申请日：2010-05-12

    申请人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： H01L21/00

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

    摘要： A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by a first pad region and a second pad region, forming a gate around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate structure and around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the exposed nanowire, removing a second portion of the exposed nanowire to form a cavity defined by the core portion of the nanowire surrounded by the gate structure and the spacer, exposing a silicon portion of the substrate, and epitaxially growing a doped semiconductor material in the cavity from exposed cross section of the nanowire, the second pad region, and the exposed silicon portion to connect the exposed cross sections of the nanowire to the second pad region.

    摘要翻译： 形成纳米线隧道场效应晶体管（FET）器件的方法包括形成由第一焊盘区域和第二焊盘区域悬挂的纳米线，在纳米线的一部分周围形成栅极，形成邻近栅极侧壁的保护隔离层 结构和纳米线的周围部分从栅极结构延伸，将离子注入暴露的纳米线的第一部分中，去除暴露的纳米线的第二部分以形成由栅极结构包围的纳米线的核心部分限定的空腔，以及 所述间隔物暴露所述衬底的硅部分，以及从所述纳米线，所述第二焊盘区域和暴露的硅部分的暴露截面外延生长所述腔中的掺杂半导体材料，以将所述纳米线的暴露的横截面与 第二垫区域。

    Nanowire Tunnel Field Effect Transistors
    65.
    发明申请
    Nanowire Tunnel Field Effect Transistors 有权
    纳米线隧道场效应晶体管

    公开(公告)号：US20120273761A1

    公开(公告)日：2012-11-01

    申请号：US13541022

    申请日：2012-07-03

    申请人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： H01L29/775 ,  B82Y99/00

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

    摘要： A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.

    摘要翻译： 纳米线隧道场效应晶体管（FET）器件包括沟道区域，该沟道区域包括具有第一远端和第二远端的硅部分，硅部分被围绕硅部分周向设置的栅极结构围绕，漏极区域包括 从第一远端延伸的掺杂硅部分，布置在沟道区域中的掺杂硅部分的一部分，由硅部分的第二远端限定的空腔和栅极结构的内径，以及源区域， 从空腔中的硅部分的第二远端外延延伸的掺杂外延硅部分，第一焊盘区域和硅衬底的一部分。

    Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors
    67.
    发明授权
    Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors 有权
    嵌入式DRAM集成电路，具有极薄的绝缘体上硅传导晶体管

    公开(公告)号：US07985633B2

    公开(公告)日：2011-07-26

    申请号：US11929943

    申请日：2007-10-30

    申请人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

    发明人： Jin Cai ,  Josephine Chang ,  Leland Chang ,  Brian L. Ji ,  Steven John Koester ,  Amlan Majumdar

    IPC分类号： H01L21/84

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10894

    摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

    摘要翻译： 提供具有组合的存储器和逻辑功能的集成电路。 一方面，提供集成电路。 集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。