公开(公告)号：US07271444B2

公开(公告)日：2007-09-18

申请号：US10732958

申请日：2003-12-11

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

IPC分类号： H01L29/76

CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with an silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

摘要翻译： 形成具有环绕，垂直排列的双栅电极的场效应晶体管。 从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边。 第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。 第二次回蚀将栅极导体材料的一部分移除第二距离。 第一和第二距离之间的差异定义了最终设备的栅极长度。 剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

公开(公告)号：US07265013B2

公开(公告)日：2007-09-04

申请号：US11162662

申请日：2005-09-19

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Kirk D. Peterson

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Kirk D. Peterson

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132

摘要： A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed on exposed-to-ambient surfaces of the structure. Then, portions of the conformal protective layer are removed so as to expose the capping region to the surrounding ambient without exposing the memory region to the surrounding ambient. Then, the capping region is removed so as to expose the positioning region to the surrounding ambient. Then, the positioning region is removed so as to expose the memory region to the surrounding ambient. Then, the memory region is directionally etched with remaining portions of the conformal protection layer serving as a blocking mask.

摘要翻译： 一种结构制造方法。 该方法包括提供一种结构，该结构包括：（a）待蚀刻层，（b）存储区域，（c）位于彼此顶部的定位区域（d）和封盖区域。 然后，定位区域缩进。 然后，在结构的暴露于环境的表面上形成保形层。 然后，去除保形层的一部分，以将覆盖区域暴露于周围环境，而不会使存储区域暴露于周围环境。 然后，去除封盖区域，以将定位区域暴露于周围环境。 然后，移除定位区域，以将存储区域暴露于周围环境。 然后，存储区域被定向蚀刻，保形层的剩余部分用作阻挡掩模。

公开(公告)号：US20070184588A1

公开(公告)日：2007-08-09

申请号：US11735075

申请日：2007-04-13

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： H01L21/84

CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

摘要翻译： 形成具有环绕，垂直排列的双栅电极的场效应晶体管。 从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。 第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。 第二次回蚀将栅极导体材料的一部分移除第二距离。 第一和第二距离之间的差异定义了最终设备的栅极长度。 剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

公开(公告)号：US20070170516A1

公开(公告)日：2007-07-26

申请号：US11340344

申请日：2006-01-26

申请人： Delbert Cecchi ,  Toshiharu Furukawa ,  Jack Mandelman

发明人： Delbert Cecchi ,  Toshiharu Furukawa ,  Jack Mandelman

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L27/0921 ,  H01L27/0928 ,  H01L29/1087 ,  H01L29/7833

摘要： A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.

摘要翻译： 具有减小的闩锁磁化率的三阱CMOS结构和制造该结构的方法。 该方法包括在P阱下形成具有低电阻的掩埋P型掺杂层和形成CMOS晶体管的N阱，并在P阱中形成的掩埋N型掺杂层中形成间隙， 在与P阱的接触下对齐的间隙。 埋入的P型掺杂层和掩埋N型掺杂层中的间隙允许在CMOS晶体管的寄生双极晶体管周围的低电阻空穴电流路径。

公开(公告)号：US20070145373A1

公开(公告)日：2007-06-28

申请号：US11684306

申请日：2007-03-09

申请人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

发明人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

IPC分类号： H01L31/00 ,  C30B21/04 ,  H01L29/04 ,  H01L29/00

CPC分类号： H01L29/045 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.

摘要翻译： 本发明提供一种用于制造包括底部半导体层的混合衬底的外延压印工艺; 存在于所述底部半导体层顶部的连续掩埋绝缘层; 以及存在于所述连续掩埋绝缘层上的顶部半导体层，其中所述顶部半导体层包括具有不同晶体取向的分离的平面半导体区域，所述分开的平面半导体区域彼此隔离。 利用外延生长，晶片接合和再结晶退火的本发明的外延印刷方法。

公开(公告)号：US07176089B2

公开(公告)日：2007-02-13

申请号：US10853177

申请日：2004-05-26

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

IPC分类号： H01L21/336

CPC分类号： H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

摘要： A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

摘要翻译： 一种制造方法提供特别适用于高密度积分的垂直晶体管，其包括通过在沟槽中蚀刻或外延生长而形成的半导体柱的相对侧上的潜在独立栅极结构。 栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。 通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。 柱的上端由盖​​和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。 在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

公开(公告)号：US07160771B2

公开(公告)日：2007-01-09

申请号：US10724483

申请日：2003-11-28

申请人： Anthony I-Chih Chou ,  Michael Patrick Chudzik ,  Toshiharu Furukawa ,  Oleg Gluschenkov ,  Paul Daniel Kirsch ,  Byoung Hun Lee ,  Katsunori Onishi ,  Heemyoung Park ,  Kristen Colleen Scheer ,  Akihisa Sekiguchi

发明人： Anthony I-Chih Chou ,  Michael Patrick Chudzik ,  Toshiharu Furukawa ,  Oleg Gluschenkov ,  Paul Daniel Kirsch ,  Byoung Hun Lee ,  Katsunori Onishi ,  Heemyoung Park ,  Kristen Colleen Scheer ,  Akihisa Sekiguchi

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/823462 ,  H01L21/823857

摘要： Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.

摘要翻译： 通过在衬底的顶表面上形成第一栅极氧化物，在半导体衬底上形成具有不同厚度的栅极氧化物，在第一栅极氧化物的选定区域上形成牺牲性硬掩模; 然后形成第二栅极氧化物。 可以在硬掩模下的第一栅极氧化物上形成第一多晶硅层。 在去除硬掩模之后，可以在第二栅极氧化物之上和第一多晶硅层上形成第二多晶硅层。 这使得能够使用高k电介质材料，并且第一栅极氧化物可以比第二栅极氧化物薄。

公开(公告)号：US07135773B2

公开(公告)日：2006-11-14

申请号：US10787640

申请日：2004-02-26

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell ,  Stanislav Polonsky

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III ,  Mark Eliot Masters ,  Peter H. Mitchell ,  Stanislav Polonsky

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： B82Y10/00 ,  H01L21/28562 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

摘要： Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

摘要翻译： 集成电路中的导电路径使用嵌入导电金属中的多个未分化碳纳米管形成，优选为铜。 优选地，导电路径包括在导电层之间运行的通孔。 优选地，通过在通孔位置的导体上形成金属催化剂垫，沉积和蚀刻介电层以形成空腔，在空腔中的催化剂上基本上平行地生长碳纳米管，并填充其中的剩余空隙来形成复合通孔 有铜的腔。 然后在通孔上形成下一导电层。

公开(公告)号：US07129138B1

公开(公告)日：2006-10-31

申请号：US11106004

申请日：2005-04-14

申请人： Toshiharu Furukawa ,  Carl John Radens ,  William Robert Tonti ,  Richard Quimby Williams

发明人： Toshiharu Furukawa ,  Carl John Radens ,  William Robert Tonti ,  Richard Quimby Williams

IPC分类号： H01L21/762

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/928 ,  H01L2924/00

摘要： Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.

摘要翻译： 提供了增强的绝缘体上硅（SOI）掩埋氧化物（BOX）结构和方法来实现增强的SOI BOX结构。 将氧注入步骤从背面进行到薄化的硅衬底层。 退火步骤从硅衬底层中的氧注入形成厚的掩埋氧化物（BOX）区域。 氧注入步骤在氧植入物附近形成隔离区域。 背侧注入步骤选择性地掺杂用于形成包括所选择的抗熔丝（AF）器件的SOI器件的SOI器件的隔离区域以及包括PFET和NFET器件的SOI晶体管的隔离区域。

公开(公告)号：US20060169972A1

公开(公告)日：2006-08-03

申请号：US10906016

申请日：2005-01-31

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

IPC分类号： H01L29/06

CPC分类号： H01L27/0688 ,  B82Y10/00 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823487 ,  H01L27/0705 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/057 ,  Y10S977/938

摘要： A hybrid semiconductor structure which includes a horizontal semiconductor device and a vertical carbon nanotube transistor, where the vertical carbon nanotube transistor and the horizontal semiconductor device have at least one shared node is provided. The at least one shared node can include, for example, a drain, source or gate electrode of a FET, or an emitter, collector, or base of a bipolar transistor. A method of forming the inventive hybrid semiconductor structure having at least one shared node between the vertical carbon nanotube transistor and the horizontal semiconductor device is also provided.

摘要翻译： 提供一种混合半导体结构，其包括水平半导体器件和垂直碳纳米管晶体管，其中垂直碳纳米管晶体管和水平半导体器件具有至少一个共享节点。 至少一个共享节点可以包括例如FET的漏极，源极或栅极电极，或双极晶体管的发射极，集电极或基极。 还提供了形成本发明的混合半导体结构的方法，该结构在竖直碳纳米管晶体管和水平半导体器件之间具有至少一个共享节点。