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    Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby
    3.
    发明授权
    Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby 有权
    用于分别优化同一半导体芯片内的PMOS和NMOS晶体管的薄栅极电介质及其制造的器件的方法

    公开(公告)号：US06821833B1

    公开(公告)日：2004-11-23

    申请号：US10605110

    申请日：2003-09-09

    申请人： Anthony I-Chih Chou ,  Toshiharu Furukawa ,  Patrick R. Varekamp ,  Jeffrey W. Sleight ,  Akihisa Sekiguchi

    发明人： Anthony I-Chih Chou ,  Toshiharu Furukawa ,  Patrick R. Varekamp ,  Jeffrey W. Sleight ,  Akihisa Sekiguchi

    IPC分类号： H01L218238

    CPC分类号： H01L21/28202 ,  H01L21/823842 ,  H01L21/823857

    摘要： A method of forming CMOS semiconductor materials with PFET and NFET areas formed on a semiconductor substrate, covered respectively with a PFET and NFET gate dielectric layers composed of silicon oxide and different degrees of nitridation thereof. Provide a silicon substrate with a PFET area and an NFET area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric layer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer and the PFET gate dielectric layer can have the same thickness.

    摘要翻译： 一种形成在半导体衬底上的PFET和NFET区域的CMOS半导体材料的方法，分别覆盖由氧化硅和不同程度的氮化构成的PFET和NFET栅极电介质层。 为硅衬底提供PFET区域和NFET区域，并在其上形成PFET和NFET栅极氧化物层。 在PFET区域上方提供PFET栅极氧化物层的氮化，以在PFET区域上方形成PFET栅极电介质层上的PFET栅极电介质层，在PFET区域上方的PFET栅极电介质层中具有氮原子的第一浓度水平。 提供NFET栅极氧化物层的氮化，以在NFET区域上方形成具有与第一浓度水平不同的氮原子浓度水平的NFET栅极电介质层。 NFET栅极电介质层和PFET栅极电介质层可以具有相同的厚度。

    FORMATION OF A DISPOSABLE SPACER TO POST DOPE A GATE CONDUCTOR
    6.
    发明申请
    FORMATION OF A DISPOSABLE SPACER TO POST DOPE A GATE CONDUCTOR 审中-公开
    形成一个可打开的间隔器以打开门盖导体

    公开(公告)号：US20070205472A1

    公开(公告)日：2007-09-06

    申请号：US11697371

    申请日：2007-04-06

    申请人： David Horak ,  Toshiharu Furukawa ,  Akihisa Sekiguchi

    发明人： David Horak ,  Toshiharu Furukawa ,  Akihisa Sekiguchi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6653 ,  H01L21/28035 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed around the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion region.

    摘要翻译： 提供了在半导体器件上形成掺杂栅极结构的方法和以该方法形成的半导体结构。 该方法包括以下步骤：提供包括栅极电介质层的半导体器件，以及在所述介电层上形成栅叠层。 后一步骤又包括以下步骤：在电介质层上形成第一栅极层，以及在第一栅极层的顶部上形成第二一次性层。 在第一栅极层和第二一次性层周围形成脂肪间隔物。 去除第二一次性层，并且将离子注入第一栅极层中以向栅极电介质层上方的栅极提供附加的掺杂剂，而脂肪一次性间隔物保持注入的离子远离临界源极和漏极扩散区域。

    Formation of a disposable spacer to post dope a gate conductor
    8.
    发明申请
    Formation of a disposable spacer to post dope a gate conductor 失效
    一次性间隔件的形成以喷涂一个栅极导体

    公开(公告)号：US20050145958A1

    公开(公告)日：2005-07-07

    申请号：US10752386

    申请日：2004-01-06

    申请人： David Horak ,  Toshiharu Furukawa ,  Akihisa Sekiguchi

    发明人： David Horak ,  Toshiharu Furukawa ,  Akihisa Sekiguchi

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/6653 ,  H01L21/28035 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed around the first gate layer and the second layers. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion region.

    摘要翻译： 提供了在半导体器件上形成掺杂栅极结构的方法和以该方法形成的半导体结构。 该方法包括以下步骤：提供包括栅极电介质层的半导体器件，以及在所述介电层上形成栅叠层。 后一步骤又包括以下步骤：在电介质层上形成第一栅极层，以及在第一栅极层的顶部上形成第二一次性层。 在第一栅极层和第二层周围形成脂肪间隔物。 去除第二一次性层，并且将离子注入第一栅极层中以向栅极电介质层上方的栅极提供附加的掺杂剂，而脂肪一次性间隔物保持注入的离子远离临界源极和漏极扩散区域。

    Formation of a disposable spacer to post dope a gate conductor
    9.
    发明授权
    Formation of a disposable spacer to post dope a gate conductor 失效
    一次性间隔件的形成以喷涂一个栅极导体

    公开(公告)号：US07229885B2

    公开(公告)日：2007-06-12

    申请号：US10752386

    申请日：2004-01-06

    申请人： David V. Horak ,  Toshiharu Furukawa ,  Akihisa Sekiguchi

    发明人： David V. Horak ,  Toshiharu Furukawa ,  Akihisa Sekiguchi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6653 ,  H01L21/28035 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed round the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion regions.

    摘要翻译： 提供了在半导体器件上形成掺杂栅极结构的方法和以该方法形成的半导体结构。 该方法包括以下步骤：提供包括栅极电介质层的半导体器件，以及在所述介电层上形成栅叠层。 后一步骤又包括以下步骤：在电介质层上形成第一栅极层，以及在第一栅极层的顶部上形成第二一次性层。 在第一栅极层和第二一次性层周围形成脂肪间隔物。 去除第二一次性层，并且将离子注入第一栅极层中以在栅极电介质层上方的栅极中提供额外的掺杂剂，而脂肪一次性间隔物保持注入的离子远离临界源极和漏极扩散区域。

    Patterned plasma nitridation for selective epi and silicide formation
    10.
    发明授权
    Patterned plasma nitridation for selective epi and silicide formation 失效
    用于选择性外延和硅化物形成的图案化等离子体氮化

    公开(公告)号：US06426305B1

    公开(公告)日：2002-07-30

    申请号：US09898202

    申请日：2001-07-03

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Akihisa Sekiguchi

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Akihisa Sekiguchi

    IPC分类号： H01L2131

    CPC分类号： H01L21/318 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/3211

    摘要： A method of selectively forming either an epi-Si-containing or a silicide layer on portions of a Si-containing substrate wherein a nitrogen-containing layer formed by a low-temperature nitridation process is employed to prevent formation of the epi-Si-containing or silicide layer in predetermined areas of the substrate. The method of the present invention includes the steps of subjecting at least one exposed surface of a Si-containing substrate to a low- temperature nitridation process so as to form a nitrogen-containing layer at or near the at least one exposed surface, wherein other surfaces of the Si-containing substrate are protected by a patterned photoresist; removing the patterned photoresist from the other surfaces of the Si-containing substrate; and forming an epi-Si-containing layer or a silicide layer on the other surfaces of the substrate which do not contain the nitrogen-containing layer. In accordance with the present invention, epi-Si-containing or silicide is not formed in areas containing the nitrogen-containing layer.

    摘要翻译： 在含Si衬底的部分上选择性地形成外延Si层或硅化物层的方法，其中通过低温氮化工艺形成的含氮层用于防止形成含外延Si 或硅化物层在基板的预定区域中。 本发明的方法包括以下步骤：使含Si衬底的至少一个暴露表面进行低温氮化处理，以便在至少一个暴露表面处或附近形成含氮层，其中其它 含Si衬底的表面被图案化的光致抗蚀剂保护; 从所述含Si衬底的其它表面去除所述图案化的光致抗蚀剂; 以及在不含有含氮层的基板的其他表面上形成外延Si层或硅化物层。 根据本发明，在含有含氮层的区域中不形成含外硅或硅化物。